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Observer
Observer
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Registered: ‎02-05-2019

Meta stability in dealing with GPIO

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Hello,

I am aware about the metastability effects and use of Double flip flop and few constaints to avoid metastability on the asynchronous signals or the signals comming for a different clock.

I was concerned that do we need to put a same double flip flop while dealing with GPIOs when we are polling its status. Every GPIO must go thorugh a double flip flop to be sure that metastability will not hit us.

Metastability.png
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369 Views
Registered: ‎07-23-2019

Re: Meta stability in dealing with GPIO

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Yes, you need similar measures for non-synchronous GPIO. Anti-metastability schemes are kind of a standard... some have more than two FFs. Not meaning the more the better, though.

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Registered: ‎07-23-2019

Re: Meta stability in dealing with GPIO

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Yes, you need similar measures for non-synchronous GPIO. Anti-metastability schemes are kind of a standard... some have more than two FFs. Not meaning the more the better, though.

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Guide
Guide
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Registered: ‎01-23-2009

Re: Meta stability in dealing with GPIO

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I was concerned that do we need to put a same double flip flop while dealing with GPIOs when we are polling its status.

So, first, the diagram you attached is a reset bridge, not a standard two stage metastability hardener - the difference is that in the reset bridge, the asynchronous signal goes so the D inputs, not the preset inputs of the flip-flops.

 

image.png

Second, yes, do need these on all asynchronous inputs - even GPIOs that are polled, unless you have "some other mechanism of guaranteeing that they are stable when you poll them".

some have more than two FFs. Not meaning the more the better, though.

Well, technically more is always better, although more is not always necessary!

The whole point of the back to back flip-flop chain is to give the metastable condition time to resolve. In many cases one clock period (minus a bit), which is the time between the sampling of the first flip-flop and the sampling of the second is sufficient; most of the time the metastable event has resolved before the second flip-flop samples it. However, if it hasn't, then the 2nd flip-flop can also go metastable, which would require a third. The determination of how many flip-flops is based on clock frequency and transition rate of the input as well as the characteristics of the flip-flops, which ultimately determines the Mean Time Between Failures of this synchronizer. If the MTBF is high enough with two FFs, then three aren't necessary, but the MTBF will always be higher with more FFs. Take a look at this post on MTBF.

Next, it is important to note that in Xilinx devices, the flip-flops in the metastability chain must all have the ASYNC_REG property set on them.

Finally if this signal is a primary input of the FPGA, you may be able to take advantage of the IDDR in SAME_EDGE_PIPELINED mode to implement the synchronizer (if 2 FFs are enough).

Avrum

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Explorer
Explorer
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Registered: ‎06-25-2014

Re: Meta stability in dealing with GPIO

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Just to add much the same in that the more registers to have chained reduces the probability (I believe exponentially) of metastability getting through each register to feed your logic.

 

It can also be argued that if your input only feeds a single point of logic that these registers are not required. (Not that I would ever recommend this) This is because metastability causes problems when a signal in a metastable condition feeds multiple blocks of logic where one block may see a '1' and another a '0' resulting in non-deterministic behaviour.  

 

At least this is how it was described to me during some Xilinx training many years back