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577 Views
Registered: ‎10-02-2019

Missing blocks

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I'm designing a complex system in Spartan7 with Verilog, in which all blocks are present except one after running implementation. I've also isolated the block in a new design, but it is also missed. Simulation runs correctly. Any idea?

Thank for your help.

Top module:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02.10.2019 17:47:42
// Design Name:
// Module Name: kkLina
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module kkLina(
input dIn,
input Clk,
input Enab,
output Out
);

Receptor rxItem(.DataIn(dIn), .ClkModem(Clk), .Enable(Enab), .Valid(Out));

endmodule

Receptor module:

`timescale 1us / 100ns

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01.10.2019 11:48:52
// Design Name:
// Module Name: Receptor
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module Receptor(
input DataIn,
input ClkModem,
input Enable,
output reg Valid
);

parameter eIni = 'b00, eEnabled = 'b01, eFinal = 'b10;

reg [1:0] estado;
reg [`NumBitsPattern - 1:0] valor;

// initial
// Valid = 0;

always @(posedge Enable or negedge ClkModem or posedge ClkModem) begin
if ((Enable == 0) && (ClkModem == 1)) begin
Valid <= 0;
estado <= eIni;
valor <= 'b000000;

end // if ((Enable == 0) && (ClkModem == 1)) begin
else begin
case (estado)
eIni: begin
if ((Enable == 1) && (ClkModem == 1))
estado <= eEnabled;

end // eIni: begin
eEnabled: begin
if ((Enable == 1) && (ClkModem == 0)) begin
valor = {valor, DataIn};

if (valor == `Pattern) begin
estado <= eFinal;
Valid <= 1;

end // if (valor == 'b10001) begin

end // if ((Enable == 1) && (ClkModem == 0)) begin

end // eEnabled: begin
eFinal: ;
default: begin
Valid <= 0;
estado <= eFinal;

end // default: begin

endcase // case (estado)

end // else begin

end // always @(posedge Enable or negedge ClkModem or posedge ClkModem) begin

endmodule // module Receptor();

module Receptor_testbench();

reg dIn;
reg clk;
reg enab;
wire valid;

Receptor testReceptor(.DataIn(dIn), .ClkModem(clk), .Enable(enab), .Valid(valid));

initial begin
clk=0;
enab = 0;
dIn = 0;

end // initial begin

initial begin: clkLoop
forever #5 clk=~clk;
end // initial begin: clkLoop

initial begin
#11 enab = 1;
#15 dIn = 1;
#10 dIn = 0;
#30 dIn = 1;
#10 dIn = 0;
#20 enab = 0;
#100 disable clkLoop;
#1 $finish;

end

endmodule // module Receptor_testbench();

 

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515 Views
Registered: ‎07-23-2019

I think your Valid signal is optimized to 0 as shown in the diagram, that could because of your comparison valor==`Pattern, I can't see that constant defined

View solution in original post

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Xilinx Employee
Xilinx Employee
561 Views
Registered: ‎05-22-2018

Hi @mheraswavenet ,

Try to apply DONT_TOUCH attribute in RTL or module block which is optimized and check whether it helps. For information on DONT_TOUCH check page no.49 of below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf 

 

Thanks,

Raj

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522 Views
Registered: ‎10-02-2019

Hi, Raj.

It doesn't work. Please, look at attached the schema it generates.

Kind regards,
Manuel Heras

schema.jpg
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Highlighted
516 Views
Registered: ‎07-23-2019

I think your Valid signal is optimized to 0 as shown in the diagram, that could because of your comparison valor==`Pattern, I can't see that constant defined

View solution in original post

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Highlighted
Moderator
Moderator
507 Views
Registered: ‎03-16-2017

Hi @mheraswavenet

Kindly modify your RTL becuase your output port "Valid" only connected with constants as shown in the Receptor RTL. 

And input port "Datain" is not provided with the proper connection. Check it in elaborated design. 

I have applied dont_touch on registers which were removed due to it's no used (code attached). Now it shows as shown below but you will still have to modify your Receptor RTL for Datain port and Valid port. 

synthde.PNG

Regards,
hemangd

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Highlighted
461 Views
Registered: ‎10-02-2019

Hi, hemanged

I've solved the problem. I don't know very well where it was, but it seems that it was related to the way in which the clocks were managed. Additionally, looking to your schematic I can note that the otuput port (Valid) still appears grounded.

Kind regards.

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