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Multiple Driver Nets

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Adventurer
Posts: 61
Registered: ‎01-05-2017
Accepted Solution

Multiple Driver Nets

 

Hi guys

 

I'm trying to design a kind of a sampler circuit and having the multiple driven nets error.

 

My purpose is building a kind of a stopwatch and start another process using the time info coming from here. But when the other process starts I want the first process to reset itself and to go on working. Problem arises because of the variable I'm using to commuinicate between two processes.

 

in brief:

Pro 1 counts until 1 sec + makes flag high

Pro 2 starts, Pro 1 reset + starts counting time again

Pro 2 ends + makes flag 0

 

p.s I didn't understand in the end of 1 second when I set flag 1 will it stay 1 or since the time counter resets itself will it be 0 even if I didn't assign this anywhere in the 1st process.

 

What I tried?? : I tried to make second process as a component or two processes two individual FSM process (attached). Both stuck at the same mid variable.

 

Any idea is very welcome :)

Thanks in advance


Accepted Solutions
Mentor
Posts: 1,364
Registered: ‎11-14-2011

Re: Multiple Driver Nets

I would have a third, synchronous, process that actually drives the flag.

 

Pro 1 asserts a single clock cycle signal to set the flag and Pro 2 asserts a single clock cycle signal to reset the flag.

 

A little like this, perhaps:

 

Pro_1 : process (clock) is

begin

  if rising_edge(clock) then

    counter <= (counter + 1) mod C_TERMINAL;

    if (counter = C_TERMINAL-1) then

      set_flag <= '1';

    else

      set_flag <= '0';

    end if;

  end if;

end process Pro_1;

 

Pro_2 : process (clock) is

begin

  if rising_edge(clock) then

    if (flag = '1') then

      -- your FSM stuff here

    end if;

    -- a little bit of pseudo-code here 

    if (pro2_end) then

      reset_flag <= '1';

    else

      reset_flag <= '0';

    end if;

  end if;

end process Pro_2;

 

Pro_3 : process (clock) is

begin

  if rising_edge(clock) then

    if (reset_flag = '1') then

      flag <= '0';

    elsif (set_flag = '1') then

      flag <= '1';

    end if;

  end if;

end process Pro_3;

 

Handshaking - it's good stuff! :)

----------
"That which we must learn to do, we learn by doing." - Aristotle

View solution in original post


All Replies
Mentor
Posts: 1,364
Registered: ‎11-14-2011

Re: Multiple Driver Nets

I would have a third, synchronous, process that actually drives the flag.

 

Pro 1 asserts a single clock cycle signal to set the flag and Pro 2 asserts a single clock cycle signal to reset the flag.

 

A little like this, perhaps:

 

Pro_1 : process (clock) is

begin

  if rising_edge(clock) then

    counter <= (counter + 1) mod C_TERMINAL;

    if (counter = C_TERMINAL-1) then

      set_flag <= '1';

    else

      set_flag <= '0';

    end if;

  end if;

end process Pro_1;

 

Pro_2 : process (clock) is

begin

  if rising_edge(clock) then

    if (flag = '1') then

      -- your FSM stuff here

    end if;

    -- a little bit of pseudo-code here 

    if (pro2_end) then

      reset_flag <= '1';

    else

      reset_flag <= '0';

    end if;

  end if;

end process Pro_2;

 

Pro_3 : process (clock) is

begin

  if rising_edge(clock) then

    if (reset_flag = '1') then

      flag <= '0';

    elsif (set_flag = '1') then

      flag <= '1';

    end if;

  end if;

end process Pro_3;

 

Handshaking - it's good stuff! :)

----------
"That which we must learn to do, we learn by doing." - Aristotle
Adventurer
Posts: 61
Registered: ‎01-05-2017

Re: Multiple Driver Nets

Hi @hgleamon1
Thank you for the answer :)

What a pity I'm little bit confused with your code. First first process is corresponding to stop watch in my design right? As I know mod operator is not synthesisable in vhdl ??

What do you mean with "FSM stuff"? I have 2 FSM: first one for the time second one another process starting with the indicator coming from first process and must be finished much earlier then it. You mean both of them?

I have one more idea as a possible solution. Between two processes I tried to use a Set-Reset flip-flop. Set comes from first pro, reset comes from 2nd pro. They don't change any variable but the these two variables met in another logic process and set/reset the flag. This is the sample design: http://allaboutfpga.com/vhdl-code-flipflop-d-t-jk-sr/
New design attached. There is some info at the top for the purpose...

Mentor
Posts: 1,364
Registered: ‎11-14-2011

Re: Multiple Driver Nets

First process is the counter. "mod" is synthesisable in VHDL - I use it for counters all the time.

 

"FSM stuff" relates to your FSM for the second process that you described "starting with the indicator" hence that FSM is valid when the "Flag" signal is active.

 

Your idea to put a flip flop between the two is almost exactly as I described - I just made it more explicit.

----------
"That which we must learn to do, we learn by doing." - Aristotle
Adventurer
Posts: 61
Registered: ‎01-05-2017

Re: Multiple Driver Nets

Hi @hgleamon1 

 

Thank you very much for your support. I realized that I made the logic wrong. Now it works :)

 

Best wishes...