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Participant liangr
Participant
3,411 Views
Registered: ‎12-22-2009

Multiple driver error for GTP implementation.

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Hi,

 

I am using sp605 board for GTP applications. During the design timing constraint setup, the tool report error message as below:

 

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Checking expanded design ...
ERROR:NgdBuild:455 - logical net 'GTP_CLK_OUT<0>' has multiple driver(s):
     pin GTPCLKOUT1<0> on block
   GTP_CORE_inst/tile0_gtp_core_wimax_i/gtpa1_dual_i with type GTPA1_DUAL,
     pin PAD on block GTP_CLK_OUT<0> with type PAD

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     1
  Number of warnings:   0

Total REAL time to NGDBUILD completion:  2 sec
Total CPU time to NGDBUILD completion:   2 sec

One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "GTP_top.bld"...

 

\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\

 

The error shows a multiple driver and this is created by the GTP IP core wizard. I traced back to the souce but there is only one output driver for the signal wire.

 

The only possibility is that the reference clock signal is also fed into the wire but it is not used in the wizard.

 

I am not sure what I can do about the codes and if anyone has the same experience then please give me some hint about it.

 

Thank you.

 

 

 

 

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Participant liangr
Participant
4,089 Views
Registered: ‎12-22-2009

Re: Multiple driver error for GTP implementation.

Jump to solution

The problem is related with DCM problem.

 

According to the article "http://www.fpgarelated.com/usenet/fpga/show/89407-1.php"

 

There is possible driver problem related with IP core generated DCM block. When I check it, there is an internal buffer, but the direction is correct (WTF is it use for?)

 

So I checked the DCM generation wizard and found the option in the draw down option list  and choose 'none' for the input clock.

 

Then the translate works.

 

It seems there is a problem with the display of the rtl schematic display, it did not show correctly the design module and then it really cost a lot of time.

 

 

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2 Replies
Participant liangr
Participant
3,397 Views
Registered: ‎12-22-2009

Re: Multiple driver error for GTP implementation.

Jump to solution

According to Xilinx Error Message hints. http://www.xilinx.com/support/answers/34771.htm

 

I remove the option of add I/O buffers but the problem still exist. Even more warnings comes out.

0 Kudos
Participant liangr
Participant
4,090 Views
Registered: ‎12-22-2009

Re: Multiple driver error for GTP implementation.

Jump to solution

The problem is related with DCM problem.

 

According to the article "http://www.fpgarelated.com/usenet/fpga/show/89407-1.php"

 

There is possible driver problem related with IP core generated DCM block. When I check it, there is an internal buffer, but the direction is correct (WTF is it use for?)

 

So I checked the DCM generation wizard and found the option in the draw down option list  and choose 'none' for the input clock.

 

Then the translate works.

 

It seems there is a problem with the display of the rtl schematic display, it did not show correctly the design module and then it really cost a lot of time.

 

 

0 Kudos