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muellera
Adventurer
Adventurer
6,980 Views
Registered: ‎02-22-2016

Multiple driver error within AXI interconnect IP core

Hi,

 

I have generated an axi_interconnect core which is instantiated once in my project. When running implementation I get the following error message during the placement phase (non-project flow):

 

ERROR: [DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net <const0> has multiple drivers: GND/G, i_axi_arbiter_0/U0/i_axi_interconnect_0/inst/axi_interconnect_inst/crossbar_samd/gen_samd.crossbar_samd/gen_crossbar.addr_arbiter_ar/gen_arbiter.m_mesg_i_reg[35]/Q, i_axi_arbiter_0/U0/i_axi_interconnect_0/inst/axi_interconnect_inst/crossbar_samd/gen_samd.crossbar_samd/gen_crossbar.addr_arbiter_aw/gen_arbiter.m_mesg_i_reg[35]/Q.

I'm a little puzzled, because the problem refers to a net deeply within the axi_interconnect core. At the moment I guess that this may be related to the fact that some of the axi slave ports of the axi_interconnect are not actually used but are connected to constant '0' or left open. Any suggestions?

I could not find any known issues about this.

 

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6 Replies
u4223374
Advisor
Advisor
6,977 Views
Registered: ‎04-26-2015

I'd guess that you've connected an output from one of the AXI Slave ports to "const0" (ie constant zero). As a result, "const0" is being driven both by GND (by definition) and by that output, which is obviously not allowed.

 

The obvious fixes are to either leave the ports completely disconnected, or resize the AXI interconnect so those ports just don't exist.

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balkris
Xilinx Employee
Xilinx Employee
6,969 Views
Registered: ‎08-01-2008

the DRC message tells you that there are multiple drivers for const0 signal.

check the assignment for this signal or share code
Thanks and Regards
Balkrishan
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muellera
Adventurer
Adventurer
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Registered: ‎02-22-2016

@u4223374: There is no signal called "const0", I assume this is a net inferred during synthesis.
There are some unused AXI slave interfaces where input ports are
connected to '0' or (others => '0') and outputs are left open. This should be the
correct way to handle unused ports in VHDL.
There is no constant '0' or the like connected to any output port,
also this would already cause an error during elaboration or synthesis I guess.

@balkris: As I said, the error message refers to a signal deeply within the
AXI interconnect IP core which I generated using Vivado.
I did not write that code and thus assume the cause of the problem is in the external port connections or some synthesis parameter..

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balkris
Xilinx Employee
Xilinx Employee
6,941 Views
Registered: ‎08-01-2008

you may share your project . Not sure what going wrong here
Thanks and Regards
Balkrishan
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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012

this error happens when you connect an output to a wire which is also assigned to 0 ie
wire foo = 0;
axi_ic u0(.axi_out_bar(foo), ...);
you don't need to assign unneeded outputs. It might be difficult figure out how the output is being connected to ground but you should start disconnecting outputs.
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twdahlin
Visitor
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Registered: ‎02-19-2018

I came across this DRC error using 2019.1.3 where VHDL had default signal assignments driving IP outputs.

The same design under 2019.1.2 did not issue the same DRC errors.

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