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Observer asenapati
Observer
2,413 Views
Registered: ‎06-01-2016

Multiply by 4 clock using virtex5 (input clk frequency=6.144MHz)

Is it possible to generate a 4*6.144MHz clock from 6.144MHz input clock using PLL in Virtex5 FPGA? I noticed that Input clock frequency minimum limit is 19MHz. I just want to confirm it, if it's impossible to generate multiply by 4 clock from 6.144MHz input clock.

(N.B.- There is a reason for not generating 6.144MHz clock from 4*6.144MHz clock.)

 

Thanks.

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Guide avrumw
Guide
2,398 Views
Registered: ‎01-23-2009

Re: Multiply by 4 clock using virtex5 (input clk frequency=6.144MHz)

As you noted, the Finmin of the V5 PLL is 19MHz, so you cannot work with a 6.144MHz CLKIN.

 

The DCM in "DFS mode only" (where you only use CLKFX and CLKFX180, and none of CLK0, CLK90... CLK2x) can accept a clock as low as 1MHz, but even in this mode, the minimum output frequency is 32MHz (which is less than the 24.6MHz you need). So, you could (say) multiply the 6.144 by 8 in the DCM, and then divide it by 2 with either

  - a PLL (which might not be a bad thing, since this will filter some of the jitter coming from the DCM), or

  - a BUFGCE

 

So, its messy, but possible...

 

Avrum

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