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Observer magjan
Observer
13,648 Views
Registered: ‎02-17-2008

Multithreading map and par in ISE 11.2 for Windows

I found this thread: "multi-threaded map and par in ISE 11."

that talks about multithreading support under Linux from ISE v11.1 (or actually the lack thereof). My question is that I've read that also the Windows version of ISE got support for multithreading PAR in version 11.2. Today I've downloaded the ISE Webpack v11.1, applied the v11.2 patch and tried one of my bigger build (A Math problem-solver engine) on it. To my disappointment none of the processes that are used in ISE (ise.exe map.exe par.exe and others) are running more than 50%. Which actually means that none of the steps involving building FPGA-binaries are accelerated b y a Dual-machine like the one I've got. It would be nice to hear from Xilinx (or any of you here at the forum), if there is some articles to be found on this subject or if it actually a feature that are begin implemented right as we speak.

Just as a sidenote I can see that some of the tools within the ISE Webpack is built with Visual Studio 2005 AND seem to use the openmp.dll that ships with Visual Studio which is a GOOD thing. That would be the perfect implementation tool for a multithreaded/scalable PAR algoritm..

 

But the actual outcome of the build looks good. I build the math-engine for my S3E-1600E circuit and the settings may not be exactly the same but pretty close I think. Remember that I've haven't done any Floorplanning or setting any Constraints at all beside a 40Mhz main clk constraint that it manages without problems. So for people more familiar with the environment the result may be better:

 

10.1:

Flip-flops 1,972 (6%)
4-input LUTs 12,350 (41%)

Total Slices used: 6,837 (46%)

Total 4-input LUTs: 8,324 (28%)

 

11.2:

Flip-flops: 3,484 (11%)

4-input LUTs 7,321 (24%)

Total Slices used: 5,403 (36%)

Total 4-input LUTs: 13,041 (44%)

 

That's a pretty good shave-off I think. The normal case in earlier Webpacks (at least for me) is that alot of flip-flops goes unused but this looks good.

 

Any comments on Multithreading and/or the numbers above?

 

Message Edited by magjan on 07-02-2009 01:12 PM
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8 Replies
Advisor evgenis1
Advisor
13,645 Views
Registered: ‎12-03-2007

Re: Multithreading map and par in ISE 11.2 for Windows

I compiled three large Virtex5 designs on 10.1 and 11.2. The logic utilization in both cases was very close. I can attest that the compile time and memory usage went significantly down in 11.2. 

I cannot explain why in your case 11.2 synthesized the design with 20% less slices than 10.1.

 

 

 OutputLogic

 

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Xilinx Employee
Xilinx Employee
13,593 Views
Registered: ‎07-30-2007

Re: Multithreading map and par in ISE 11.2 for Windows

From the Command Line Tools User Guide (PAR Chapter, Options section):

 

-mt (Multi-Threading)

 

Syntax
-mt {on |off }.

 

This option tells PAR how many processors it should use and includes multi-threading capabilities in both the
Placer and the Router. The -mt off option will use one processor.

 

The last sentence is not clear on the number of processors supported, but I believe it is only 2 at this point.

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Xilinx Employee
Xilinx Employee
13,588 Views
Registered: ‎11-28-2007

Re: Multithreading map and par in ISE 11.2 for Windows

Multithreading shouldn't make that big of a difference in FF/LUT counts. What're the device utilizations after synthesis in both versions?

 

Cheers,

Jim

 

Cheers,
Jim
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Observer magjan
Observer
13,572 Views
Registered: ‎02-17-2008

Re: Multithreading map and par in ISE 11.2 for Windows

After I posted the original message while waiting for response I tried to add the "-mt" parameter by adding it to "Other Place & Route Command Line Options" under the "Place And Route Properties" inside the ISE environment but ISE gives me the error message:

 

-snip-

Release 11.2 - par L.46 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
ERROR:Portability:90 - Command line error: Switch "-mt" is not allowed.

-snip-

 

So either I'm not doing it right or it isn't supported..

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Observer magjan
Observer
13,570 Views
Registered: ‎02-17-2008

Re: Multithreading map and par in ISE 11.2 for Windows

jimwu, 

 

Sorry for bringing up 2 separate things in the same post and confuse, but it was suppose to include both "the good" and "the bad" I found about ISE Webpack 11.2 for a nuanced picture. So to try and make everything clearer I both add some more info on the first post and specify some questions.

 

1) Has the free Xilinx ISE Webpack v11.2 for Windows really support for using multiple cores when performing "Place And Route"?

2) If so, how do I enable it? Because out-of-the-box is does not use more than 1 core.

 

Some more info about the actual math-engine synthesis. When I did my first 2 runs I did not do exactly the same in 10 and 11. I accidentally changed the timing (and maybe more) in-between runs because it did not manage to cope with my timing-requirements.

I'll do it all over again for a more fair comparison:

 

Timing constraints on main clock is set to 40Mhz which both 10.1.3 and 11.2 does without problems.

 

ISE 10.1.3:

 

Timed run:

Synth:           2min 30secs

PAR+Other: 4min 41secs 

TOTAL time: 7min 11secs

 

Device utilization summary (synth):
---------------------------

Selected Device : 3s1600efg320-4

 Number of Slices:                      4589  out of  14752    31% 
 Number of Slice Flip Flops:       3485  out of  29504    11% 
 Number of 4 input LUTs:            8689  out of  29504    29% 
    Number used as logic:            8621
    Number used as RAMs:          68
 Number of IOs:                          19
 Number of bonded IOBs:           15  out of    250     6% 
    IOB Flip Flops:                        1
 Number of BRAMs:                    7  out of     36    19% 
 Number of MULT18X18SIOs:    2  out of     36     5% 
 Number of GCLKs:                    4  out of     24    16% 
 Number of DCMs:                      1  out of      8    12% 

 

ISE 11.2:

 

Timed run:

Synth:            2min 00secs

PAR+Other:  7min 44secs 

TOTAL time: 9min 44secs

 

Device utilization summary (synth):

---------------------------

 

Selected Device : 3s1600efg320-4

 

Number of Slices:                4559 out of 14752 30%

Number of Slice Flip Flops: 3490 out of 29504 11%

Number of 4 input LUTs:      8630 out of 29504 29%

Number used as logic:         8562

Number used as RAMs:       68

Number of IOs:                     19

Number of bonded IOBs:      15 out of 250 6%

IOB Flip Flops:                        1

Number of BRAMs:                  7 out of 36 19%

Number of MULT18X18SIOs: 2 out of 36 5%

Number of GCLKs:                  4 out of 24 16%

Number of DCMs:                    1 out of 8 12%

 

So my initial report was not correct about 11 building much smaller cores.. sorry to say! And also the claim for faster builds seem to be something that isn't true for every build.

 

Best Regards

Magnus

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Advisor evgenis1
Advisor
13,568 Views
Registered: ‎12-03-2007

Re: Multithreading map and par in ISE 11.2 for Windows

"Command Line Tools User Guide" describes "-mt" PAR option. But if you call PAR from command-line (WIndows), "-mt" is not there.

 

OutputLogic 

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Newbie mullu
Newbie
9,529 Views
Registered: ‎04-30-2011

Re: Multithreading map and par in ISE 11.2 for Windows

hi 

I am a student doing my dissertation and I d like some info about the code for instantiating the MULT18X18SIO. 

I am using such mutipliers without clock. Do you have any idea about the instantiating code cause I got mixed up.

Thanks for your time. 

 

Christian Mugliette

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Participant shantesh
Participant
9,503 Views
Registered: ‎05-11-2010

Re: Multithreading map and par in ISE 11.2 for Windows

-mt switch for PAR was introduced in 12.X I believe. So if you build your design in the newer version, you should be able to use that option

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