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Participant alexisgrytalms
Participant
215 Views
Registered: ‎04-07-2019

My logic is scattered without any reason and doesn't meet timing.

I'm instanciating 4 GTYs and they are linked two by two.

1. topleft X0Y10, X0Y11: correctly placed and routed, meet timing

2. bottom X0Y7, X0Y8: scattered far from the GTY's locations, can't meet timing

image.png

By setting a pBlock region close to the GTYs, the placement is correct and I can meet timing easily.

My question is why do I need to use pBlock to constrain a so easy situation?

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7 Replies
Moderator
Moderator
159 Views
Registered: ‎01-16-2013

Re: My logic is scattered without any reason and doesn't meet timing.

@alexisgrytalms 

 

Did you try different placer directives? Can you share the post opt dcp file which has pblock?

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Xilinx Employee
Xilinx Employee
143 Views
Registered: ‎03-29-2013

Re: My logic is scattered without any reason and doesn't meet timing.

Which Vivado release are you using?

Vivado placer has special rules for BUFG_GT load placement based on its fanout. It is possible that this mechanism did not kick in for some of the clocks if fanout is higher than a predetermined limit, in which case the loads can move anywhere in the device. Usually, timing will help guiding the solution but in your case, it does not seem to be able to do that. Are there other physical constraints? Is the GT logic interacting with some regular IOs?

Please share a post-place report_clock_utilization report if the DCP cannot be shared.

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Participant alexisgrytalms
Participant
119 Views
Registered: ‎04-07-2019

Re: My logic is scattered without any reason and doesn't meet timing.

Thank you for your help.

I'm using 2019.1 with vu37p.

 

I haven't tried a different placer directives. (just different implementation using phy_opt that didn't solve the problem)

It seems the problem is due to the SLR crossing. Both transceivers are in a different SLR and somehow Vivado doesn't know how to place correctly. We can clearly see the "mirror" of the logic.Adding a pblock forces vivado to place the logic in one SLR rather than spread over.

I believe  I'll have to kinda manually interact everytime an SLR crossing happens.

I was more curious of the reason why Vivado can't behave correctly here for a simple desogn rather than a real problem.

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Voyager
Voyager
96 Views
Registered: ‎06-20-2017

Re: My logic is scattered without any reason and doesn't meet timing.

Just to chime in, in general, SLR crossings are tricky, and need to be handled carefully by the user, and it is best to consider SLRs vis a vis your logic before a pinout is selected and a board is fabricated.  This is covered in the ultrafast design methodology.  If you already have a board designed and PCB fab'd and assembled, it may be too late for you to make it easy on yourself and the tools, but I am posting this for the benefit of others who may come across this post before it is too late.  I think you are correct though that in this situation you may have to manually take measures to help the tool meet timing.

 


@alexisgrytalms wrote:

Thank you for your help.

I'm using 2019.1 with vu37p.

 

I haven't tried a different placer directives. (just different implementation using phy_opt that didn't solve the problem)

It seems the problem is due to the SLR crossing. Both transceivers are in a different SLR and somehow Vivado doesn't know how to place correctly. We can clearly see the "mirror" of the logic.Adding a pblock forces vivado to place the logic in one SLR rather than spread over.

I believe  I'll have to kinda manually interact everytime an SLR crossing happens.

I was more curious of the reason why Vivado can't behave correctly here for a simple desogn rather than a real problem.


 

Mike
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Participant alexisgrytalms
Participant
92 Views
Registered: ‎04-07-2019

Re: My logic is scattered without any reason and doesn't meet timing.

Exactly, I'm new in ultrascale+ and I'm using the vcu128 Xilinx evaluation board (vu37p). 3 QSFPs are located in SLR2 and 1 QSFP is located in SLR1..

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Participant alexisgrytalms
Participant
72 Views
Registered: ‎04-07-2019

Re: My logic is scattered without any reason and doesn't meet timing.

@frederi @syedz  I'm still curious, here is the clock report, there is nothing secret, I'm almost only using Xilinx's 10/25G IP core.

Thank you!

 

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Xilinx Employee
Xilinx Employee
39 Views
Registered: ‎03-29-2013

Re: My logic is scattered without any reason and doesn't meet timing.

Thanks for sharing the report. This confirms there are no additional constraints at play, and the clock nets fanout are low enough to trigger GT IP special placement. What's preventing optimal placement is the fact that the lower pair of GTYs are placed across the SLR boundary, in which case the generic placement strategy applies. The design should still meet timing though, unless the IPs don't have sufficient pipelining. Could you please share this example design since it is made of Xilinx IPs? Post-opt DCP is ok, or IPI bd file would work too (write_bd_tcl)?

Thanks!

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