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Visitor vilagjarta
Visitor
6,668 Views
Registered: ‎08-23-2013

Newbie for RLOCs

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Hi there, 

 

I am experimenting with RLOCs as part of a research project. The Mapping phase keeps me warning that these are ignored:

 

"Map:91 - MIN1 symbol "node1" has an RLOC attribute but the attribute will be ignored because the hierarchy contains no symbols with RLOC attributes."

 

I am quite new to the use of RLOCs, and only a beginner in VHDL (coming from a software community), could anyone help me out here?  I insert a minimal setting that illustrates the problem.

 

This is my submodule that I instantiate in the top module:

 

entity MIN1 is -- c gets the MINIMUM of the inputs
  port (
	 a,b: in std_logic_vector(3 downto 0);
         c: out std_logic_vector(3 downto 0)
	 ); 
end entity MIN1;
architecture bh_MIN1 of MIN1 is
begin 
   c<=a when (a<b) else
 	 b;
end architecture bh_MIN1; -- MIN1

 

 Then my top module instantiates this amongst others:

 

entity topmodule is
port (
 a: in std_logic_vector(3 downto 0);
 b: in std_logic_vector(3 downto 0);
 c: out std_logic_vector(3 downto 0);
 d: out std_logic_vector(3 downto 0)
 );
end entity topmodule;

architecture struct of topmodule is	
component MIN1 is
 port (
 a: in std_logic_vector(3 downto 0);
 b: in std_logic_vector(3 downto 0);
 c: out std_logic_vector(3 downto 0)
 );
end component MIN1;

...

type signal_type is array (0 to 3) of std_logic_vector(3 downto 0);
signal v : signal_type;	
attribute RLOC: string;
attribute RLOC of node1: label is "X0Y1";
begin
    node1: MIN1 port map (a => v(0), b => v(1), c=> c);
...
end architecture topmodule;

 

As I understand the RLOC defined in the top module becomes useless for the mapping as no RLOCs are defined in MIN1. But how can I define there RLOCs, if I can at all.

 

Do I have to define RLOCs for primitives at the lowest level as going down the hierarchy so that the actual propagation of RLOCs as explained in the XCG whould make sense?

 

Thanks!

 

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1 Solution

Accepted Solutions
Visitor vilagjarta
Visitor
10,460 Views
Registered: ‎08-23-2013

Re: Newbie for RLOCs

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Thanks!

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4 Replies
Community Manager
Community Manager
6,660 Views
Registered: ‎06-14-2012

Re: Newbie for RLOCs

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This message indicates that a hierarchy block was found to have an RLOC constraint, but no corresponding symbols with RLOC constraints were found within the hierarchy.

For that reason, the RLOC constraint on the hierarchy is ignored.

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Visitor vilagjarta
Visitor
6,645 Views
Registered: ‎08-23-2013

Re: Newbie for RLOCs

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Hi,

 

thanks for your reply. I somewhat understood that this is the problem. But I am not quite sure how to attach RLOC in the hierarcy in the given example.

 

Thanks!

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Xilinx Employee
Xilinx Employee
6,631 Views
Registered: ‎07-01-2008

Re: Newbie for RLOCs

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RLOCs are different than most constraints in that they accumulate between hierarchies rather that propagating. This allows you to create small macros that become building blocks for a larger macros. There needs to be an RLOC at the instance level and then RLOC values from the hierarchies above will be added to that value until there is a hierarchy with no RLOC. In other words there needs to be an unbroken string of RLOCs on hierarchies for them all to accumulate.

 

The question of how to apply RLOCs to inferred logic in the source is a synthesis question and has been covered in other threads. One of them points to this useful article:

http://www.fpga-dev.com/rloc-attributes-on-inferred-logic/

 

 

Visitor vilagjarta
Visitor
10,461 Views
Registered: ‎08-23-2013

Re: Newbie for RLOCs

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Thanks!

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