06-06-2010 11:34 PM - edited 06-07-2010 11:16 AM
I am very new to logic design so bare with me if I am missing something obvious or doing something stupid, any help would be much appreciated.
I have started a simple schematic design in ISE 12.1 (I know schematic designs are not a good way to design logic but I will rewrite the design in VHDL as I learn the language). The design is working in simulation but from what I can tell it does not work post-fit simulation. There are far too many signals in the post-fit simulation to get a good handle on what is going on.
I have a Digilent XC2XL and CoolRunner-II starter kit, and am starting with trying to implement the design on a XC9500XL device. Here are the questions I have \ problems I am running into.
1) I have tied a net to VCC in the schematic and when I implement the design I get the following warning. "WARNING:Cpld:828 - Signal 'Status0Out<0>.RSTF' has been minimized to 'GND'." Why is minimizing the signal to ground when it is tied to VCC? Attached is a picture of the part of my design this warning applies too and inside the "StatusReg" component.
2) I trigger many of the latches and other components in the design on edges of inputs signals that are not synchronous clocks. The compiler is yelling at me for not assigning timing constraints to these trigger signals.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1002 = PERIOD:PERIOD_RD_N:0.000 nS
because of one of the following: (a) a signal name was not found; (b) a
signal was removed or renamed due to optimization; (c) there is no path
between the FROM node and TO node in the TIMESPEC.
When I go into the constraints editor it wants me to assign a period and duty cycle for the clock but since it is an asynchronous edge trigger what am I suppose to assign this to?
3) The design is mostly asynchronous and has one synchronous clock for a few components. When I run a post fit simulation many of the asynchronous signals do not change until I clock the one synchronous clock input signal that is not tied to any of these components of the design. I have tries un-checking the "Use Global Clocks" option with no change.
Thanks in advance for any help!
Edit: Right click on the image and select view image to see it full size (firefox) or save it to desktop then open it.
Edit 2: The attachement below is not the full design.
06-07-2010 02:37 AM
When you put a FFs D-input to a constant (here VCC) the FF will be optimized away.
The message is about what happened to the Reset input :'Status0Out<0>.RSTF'.
2) Yes, because the tool sees these lines as Clock lines.
For CPLDs this might be OK (due to limited ressources).
Just enter some value to the constraints file (e.g. the same as for your clock. if you have any).
3) In your schematic you aren't using PHI_CLK at all, and the storage elements are just latches, so I have no Idea why it shouldn't work as intended.
Have you taken a look "inside" the chip? You would use fpga-editor for that purpose on FPGAS, there's a similar tool for CPLDs. Check how your Macro-Cells are internally wired up, for a better understanding of what's going on in your fitted design.
Have a nice synthesis
06-07-2010 11:15 AM - edited 06-07-2010 11:50 AM
Thanks Eilert for the response! I still have some questions \ misunderstandings.
1) Oh that makes sense, only when a global reset is present this VCC signal is ground
2) I guess I do not really understand the constraints editor. What happens if the value in the constraints editor is too slow for these asynchronous signals? Does it hurt to set the constraints faster than the signal? What is this tool really doing exactly?
3) The picture posted in the first post is not the full design. All the I\O signals are used including the PHI_CLK. There are D-flip flips in some other elements of the design that are clocked on the PHI_CLK AND\OR a few other asynchronous signals, does that change anything? How do I look inside the design layout inside the CPLD?
Thanks for any help!
Edit: I have attached a copy of the top element of my design and inside two of the blocks. It is big so you will have to right click save it to see it clearly.