cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jjcarrier
Visitor
Visitor
8,283 Views
Registered: ‎01-03-2013

NgdBuild 604 Error for Coregen IP

Jump to solution

Hi I have been trying to convert an IP core that used PLB over to AXI-Lite and I have been able to synthesize the project, but when it comes time to implement (in PlanAhead), I get the error:

 

[NgdBuild 604] logical block '<...long path...>/fifo_component' with type 'fifo_generator_v9_3' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'fifo_generator_v9_3' is not supported in target 'zynq'.

 

I also have a related critical warning:

[Designutils 20-1022] Could not resolve non-primitive black box cell 'fifo_generator_v9_3' instantiated in module '<...long path...>/fifo_component'.

 

The symbol that this error is referring to is a core generator component (the fifo generator). My PlanAhead project (NOTE: both of these cores were made using the CIP wizard in XPS) has the following folder structure (inside the pcores directory in sources_1/edk) for the AXI and PLB pcores:

 

pcores/dummy_axi_ipcore/data
pcores/dummy_axi_ipcore/devl
pcores/dummy_axi_ipcore/hdl

 

pcores/dummy_plb_ipcore/data
pcores/dummy_plb_ipcore/devl
pcores/dummy_plb_ipcore/hdl
pcores/dummy_plb_ipcore/netlist

 

Inside dummy_plb_ipcore/netlist there is the ngc file for the coregen fifo. Also inside dummy_plb_ipcore/data there is a *.bbd file that references this ngc file.

 

What is the proper way to utilize an IP core from Core Generator inside a custom peripheral using platform studio?
I suspect the issue is that PlanAhead does not know where the ngc file is, but I can't seem to find how to go about fixing this issue in PlanAhead (or XPS/CIP wizard).

 

My experience with Xilinx tools has been primarily with ISE project navigator and coregen, and I recall that you could specify a directory to search using the -sd flag in the project settings additional command options (in synthesis or implementation). I attempted to do this (although I am not sure I put the flag/path in the correct spot in the settings) and I still have the issue.

 

Any help is much appreciated.

0 Kudos
1 Solution

Accepted Solutions
jjcarrier
Visitor
Visitor
10,225 Views
Registered: ‎01-03-2013

I have resolved the issue by following this:

http://www.xilinx.com/support/answers/22882.htm

 

A question that remains is: is there a way to avoid having to do this manually? For instance, is there a tool that integrates this producure into the design flow, or do I have to do this anytime I wish to use a coregen IP inside a custom peripheral?

View solution in original post

0 Kudos
6 Replies
jjcarrier
Visitor
Visitor
10,226 Views
Registered: ‎01-03-2013

I have resolved the issue by following this:

http://www.xilinx.com/support/answers/22882.htm

 

A question that remains is: is there a way to avoid having to do this manually? For instance, is there a tool that integrates this producure into the design flow, or do I have to do this anytime I wish to use a coregen IP inside a custom peripheral?

View solution in original post

0 Kudos
hgleamon1
Teacher
Teacher
8,261 Views
Registered: ‎11-14-2011

I am not understanding you correctly, I think. Is your project targeting the AXI directories or the PLB directories? Or both?

 

If it's only AXI, then your AXI directory structure will need to match that of your PLB structure i.e. you need a netlist directory with the NGC in it.

 

Otherwise, I believe your setup for the NGC and BBD is correct for XPS. The only other thing that I can think of is that your pcore MPD needs to specify that the OPTION STYLE = MIX (or MIXED, I can never remember which one) to ensure that the tools know it is a mix of HDL and NGC files.

 

Regards,

 

Howard

 

 -- edit --

 

Ah, OK. I see you fixed it whilst I was typing. I believe the flow is correctly automated if you specify AT THE TIME OF THE PCORE CREATION that you will be using a mixed design. Otherwise, I have only ever known the manual edit.

----------
"That which we must learn to do, we learn by doing." - Aristotle
jjcarrier
Visitor
Visitor
8,253 Views
Registered: ‎01-03-2013

Thanks for the tip, where exactly would you specify that it is a mixed design? When I run through the CIP wizard to create the AXI peripheral template I did not see such an option. Is there another wizard or interface that allows you to specify this MIX option? 

0 Kudos
hgleamon1
Teacher
Teacher
8,224 Views
Registered: ‎11-14-2011

Hmm, good question. I just ran a test CIP (using XPS 13.3) and I couldn't find where to specify a mixed design, either. Must be something wrong with my memory.

 

Anyway, all I can think of is that the CIP can create the basic templates and the rest is a manual process. Can't even get any further than that with the inline help functions.

 

It isn't a massive task to create the necessary folder and files, although it would be nice to have it automated. Mildly disappointing but there you go.

----------
"That which we must learn to do, we learn by doing." - Aristotle
0 Kudos
pelagic
Contributor
Contributor
7,234 Views
Registered: ‎07-20-2012

In XPS 14.5 when running the CIP wizard you will come to step "Source File Types".   Here you may indicate the types of files that make up your peripheral.   A box for Netlist files is included.

0 Kudos
miguelalonso01
Visitor
Visitor
5,415 Views
Registered: ‎10-29-2014
You can add it directly to the core.mpd file (microprocessor description) after all Option indicators. For this you should have created a file core.bbd (black box description) which add the ngc file created by the tool coregen. Here you find them:
pcores / core / data / core.mpd
pcores / core / data / core.bbd
0 Kudos