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NgdBuild:604 - Logical block could not be resolved for UNISIM primitive

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Participant
Posts: 41
Registered: ‎03-18-2009
Accepted Solution

NgdBuild:604 - Logical block could not be resolved for UNISIM primitive

[ Edited ]

Hi 

 

I think I have an issue with paths used by ISE. It does not seem to find anything in Xilinx libraries (Unisim, Simprim etc) during ngdbuild. I get problems when I use some coregen netlists. For example I have a coregen fifo which I use and it does not seem to find Xilinx primitives:

 

 

ERROR:NgdBuild:604 - logical block
   'eqf_top_i/g1[2].pre_stc_fifo_i/rdb_fifo_inst/BU2/U0/grf.rf/mem/gbm.gbmg.gbmg
   a.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[3].ram.r/v6_noinit.ram/SDP.S
   IMPLE_PRIM36.ram' with type 'RAMB36E1' could not be resolved. A pin name
   misspelling can cause this, a missing edif or ngc file, case mismatch between
   the block name and the edif or ngc file name, or the misspelling of a type
   name. Symbol 'RAMB36E1' is not supported in target 'virtex5'.

 

My PATH variable is set correctly (XILINX_INSTALL_PATH for, example C:\Tools\Xilinx\12.1\ISE_DS). I can't find anywhere in ISE a way to see where it is expecting the unisim libraries. 

 

Note that I have build the unisim libraries at (C:\Tools\Xilinx\12.1\ISE_DS\ISE\vhdl\mti_pe\6.5c\nt\unisim) and my macro search path does point correctly to my FIFO netlist.

 

Any ideas on how to fix this will be appreciated.

Thanks,

Jaco


Accepted Solutions
Mentor
Posts: 747
Registered: ‎11-29-2007

Re: NgdBuild:604 - Logical block could not be resolved for UNISIM primitive

Are you targeting a Virtex-6 or a Virtex-5 device?

 

 

Adrian



Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).

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Mentor
Posts: 747
Registered: ‎11-29-2007

Re: NgdBuild:604 - Logical block could not be resolved for UNISIM primitive

Are you targeting a Virtex-6 or a Virtex-5 device?

 

 

Adrian



Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).
Participant
Posts: 41
Registered: ‎03-18-2009

Re: NgdBuild:604 - Logical block could not be resolved for UNISIM primitive

Aha I think you are right...

 

I'm targeting Virtex-5 at the moment but the netlist was generated for Virtex-6. I hoped that it worked for both of them since I can't launch Coregen to regenerate it. It crashes without any feedback on why it does. I even run it in command prompt with the -ddd debug switches on but still nothing...

 

Do you think thats the reason I get those NGDBuild errors?

Participant
Posts: 41
Registered: ‎03-18-2009

Re: NgdBuild:604 - Logical block could not be resolved for UNISIM primitive

Ok no that was not the problem. I regenerated the netlists for Virtex-5 on a different machine but I still get the same error messages. 

 

I get multiple messages like this, some even for other components not related to these netlists. For example I get them for our Aurora core as well.

 

 

ERROR:NgdBuild:604 - logical block
   'ROCKET_IO_LEFT/RIO_RDATA_IFACE_1/U_0/GEN_CORES[1].AURORA_CORE_VIRTEX2P_I/AUR
   ORA_VIRTEX2P_I/lane_0_mgt_i' with type 'GT_CUSTOM' could not be resolved. A
   pin name misspelling can cause this, a missing edif or ngc file, case
   mismatch between the block name and the edif or ngc file name, or the
   misspelling of a type name. Symbol 'GT_CUSTOM' is not supported in target
   'virtex5'.