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Explorer
Explorer
660 Views
Registered: ‎09-05-2015

No driver found on X

I have a function that has an input of "data_in", "rst", and "clk". What I want to do is that I want to fix all these routes.

Following the example in UG903, I am trying to fix the "data_in" first. But I've got the error below.

 

ERROR: [Designutils 20-949] No driver found on net data_in.

 

 

 

The .xdc looks like

 

 

set_property BEL C5LUT [get_cells r5_i_1]
set_property BEL G6LUT [get_cells r3_i_2]
set_property BEL H6LUT [get_cells r8_i_1]
set_property BEL C6LUT [get_cells r4_i_1]
set_property BEL H6LUT [get_cells data_out_INST_0]
set_property BEL B5LUT [get_cells r7_i_1]
set_property LOC SLICE_X53Y443 [get_cells r8_i_1]
set_property LOC SLICE_X53Y442 [get_cells r4_i_1]
set_property LOC SLICE_X53Y443 [get_cells r3_i_2]
set_property LOC SLICE_X53Y442 [get_cells r7_i_1]
set_property LOC SLICE_X53Y442 [get_cells r5_i_1]
set_property LOC SLICE_X53Y442 [get_cells data_out_INST_0]
set_property LOCK_PINS {I0:A3} [get_cells r4_i_1]
set_property LOCK_PINS {I0:A3} [get_cells r5_i_1]
set_property LOCK_PINS {I2:A1} [get_cells r8_i_1]
set_property LOCK_PINS {I4:A4} [get_cells r7_i_1]
set_property LOCK_PINS {I5:A4} [get_cells data_out_INST_0]
set_property LOCK_PINS {I5:A5} [get_cells r3_i_2]

set_property FIXED_ROUTE { { EE1_E_BEG0 { INT_NODE_IMUX_62_INT_OUT1 IMUX_W1 } INT_NODE_SDQ_49_INT_OUT1 { NN1_W_BEG1 INT_NODE_IMUX_34_INT_OUT1 BOUNCE_W_2_FT1 INT_NODE_IMUX_58_INT_OUT1 IMUX_W38 } SS1_W_BEG1 { INT_NODE_IMUX_63_INT_OUT0 { BYPASS_W3 INT_NODE_IMUX_44_INT_OUT0 IMUX_W37 } IMUX_W23 } INT_NODE_IMUX_62_INT_OUT1 IMUX_W16 } } [get_nets data_in]

 

 

Any suggestion?

 

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2 Replies
Moderator
Moderator
647 Views
Registered: ‎01-16-2013

Re: No driver found on X

@moon5756,


Can you show us the schematic of data_in net mentioned in error message?

What is the result of command "get_property ROUTE [get_nets data_in]"

 

--Syed

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Explorer
Explorer
600 Views
Registered: ‎09-05-2015

Re: No driver found on X

@syedz Thanks for the reply!

 

I've got

 

get_property ROUTE [get_nets data_in]
{}

 

what does it mean?

 

So, to explain further, the main reason I want to achieve this is that I want to remove "top implementation" process in OOC implementation in https://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug946-vivado-hierarchical-design-tutorial.pdf.

 

There is "top implementation" to route_design on the top-level, but I believe this process is theoretically unnecessary. By manually routing the nets on the pblock boundary, we should be able to skip this process.

 

 

Thanks!

 

 

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