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Observer
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Registered: ‎02-21-2019

No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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I started off with a constraints file which passed all timing requirements during Synthesis.

After Implementation there was one timing failure, and, using Vivado, I clicked on option to add it as set_false_path, which gets inserted into the file then using pre-built command, from Vivado.

However then, after I re-run Synthesis and Implementation, it fails to resolve this path at both stages, saying it cannot find the object. I've tried to entering it myself (which is of no difference, I just double checked the path as I see it reported in the Vivado anyway), with same result. Below is that spec, c & p :

 

set_false_path -from [get_ports {SWT[0]}] -to [get_pins {u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_cooolgate_en_gate_4_cooolDelFlop/D}]

 

 

And the error from Vivado is :

[Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_cooolgate_en_gate_4_cooolDelFlop/D}]'. ["/home/esembdev/wrksp_uci_x49495/dr_lab5_uut/lab5_uut.srcs/constrs_1/imports/source/nexysdemo.xdc":96]

 

How / why does it not work, any suggestions?

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Registered: ‎01-22-2015

Re: No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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@dry 

It looks like you are using Xilinx Block Memory Generator IP to get block RAM.  If you are writing timing constraints that end on pins inside this IP and you are doing Out-Of-Context (OOC) synthesis for the IP, then it is normal for project-synthesis to throw a warning about the constraint.  -because, project-synthesis cannot “see” inside IP that underwent OOC synthesis. 

If implementation does not throw a warning about a timing constraint, then you can ignore the synthesis warning about the timing constraint.

Also, do you have a reason for using the set_false_path constraint?  “My design does not pass timing analysis”, by itself, is a bad reason.   

However, maybe I can help you with a reason.  In the path that is failing timing, I see the word “coolgate” which I think is part of BRAM power optimization (a circuit that disables BRAM when it is not in use and saves electrical power).  See the following post for some details. 

https://forums.xilinx.com/xlnx/board/crawl_message?board.id=OTHERIP&message.id=3144

Also, as recommend in that post, try using the NoBramPowerOpt directive in Vivado implementation (instead of using set_false_path) to solve your timing analysis problem.  That is, using this directive may help you pass timing analysis by removing the "coolgate" path - but your FPGA might then use a little more power when running.

NoBramPowerOpt.jpg

Cheers,
Mark

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Observer
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Registered: ‎02-21-2019

Re: No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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I thought that u_rams/ root seamed to have been repeated twice, tried to cut out repeating part, but still same issue:

[Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_cooolgate_en_gate_4_cooolDelFlop/D}]'. ["/home/esembdev/wrksp_uci_x49495/dr_lab5_uut/lab5_uut.srcs/constrs_1/imports/source/nexysdemo.xdc":100]
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Observer
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Registered: ‎02-21-2019

Re: No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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Here is pic with the part of schematic showing where that problem pin is ...

problematic_pin.png
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Registered: ‎03-16-2017

Re: No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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@dry 

Open implemented design and Run get_pins u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_cooolgate_en_gate_4_cooolDelFlop/D command in tcl console and see if it returns pin name or not. 

If the pin is present in the design, the alternative way to add this false_path constraint is  - Go to Timing Constraints wizard (In Vivado GUI - flow navigator - below synthesized design or implemented design you will find constraints wizard) UG 903 can help here. 

Also, try with get_pins -hier option so you can reduce the pin's hierarchy in the constraint. 

 

 

Regards,
hemangd

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Observer
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Re: No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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@hemangd 

The get_pins command in TCL console returns nothing / error if in Synthesis Design, but  if ran in Implementation , then it seems to succeed (no error returned, returns full path queried).
The timing error/problem does occur only after Implementation. 

So how do I modify / add /remove constraint, using XDC file, if it seems not found at Synthesis? Also, appears that even if I insert it into XDC file, it still fails to work at Implementation stage.

Using Wizard:

I tried using Constraints Wizard under Implementation.  After un-ticking Hierarchy option, it found that full path to the pin, and using the wizard, it inserted the false path option into it's table, apparently with no error. After saving the changes, it wrote to the the end of my XDC file same constraint I was manually inserting before:

set_false_path -from [get_ports {SWT[0]}] -to [get_pins {u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_cooolgate_en_gate_4_cooolDelFlop/D}]

 This then, as before fails to resolve at Synthesis. But that's oK for Synthesis, as Synthesis has no timing constraints failures.

Proceeding to run Implementation, which fails as before - Failed Timing. Opening Implementation Design,  and checking Timing, shows exactly same place as before - exactly same pin/path.

Wizard or not, cannot make it disappear.

Output from TCL console under Synthesis:

set_false_path -from [get_ports {SWT[0]}] -to [get_pins {u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_cooolgate_en_gate_4_cooolDelFlop/D}]
WARNING: [Vivado 12-508] No pins matched 'u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_cooolgate_en_gate_4_cooolDelFlop/D'.
ERROR: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_pins {u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_cooolgate_en_gate_4_cooolDelFlop/D}]'.
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.

 

Output when under TCL console in Implementation:  (No output; command executes with nothing printed)

set_false_path -from [get_ports {SWT[0]}] -to [get_pins {u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/u_rams/u_ram_4dx16w_wrapper/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_cooolgate_en_gate_4_cooolDelFlop/D}]

 

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Observer
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Registered: ‎02-21-2019

Re: No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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Again at Synthesis, a query like : 

get_pins -hier -filter {NAME =~ u_rams/*/DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_*}

does not find anything.

But after Implementation Design that returns a bunch, including one I need.

So are these generated only after Implementation? How to have Implementation only constraint file - if this is would be right way to remove it.

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Registered: ‎03-16-2017

Re: No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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@dry 

Kindly share your opt.dcp (checkpoint) to analyze it further to find out the root cause behind it. You can share it via ezmove ftp which is secured ftp.

 I have sent you a test package via ezmove through which you can provide this checkpoint. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Registered: ‎01-22-2015

Re: No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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@dry 

It looks like you are using Xilinx Block Memory Generator IP to get block RAM.  If you are writing timing constraints that end on pins inside this IP and you are doing Out-Of-Context (OOC) synthesis for the IP, then it is normal for project-synthesis to throw a warning about the constraint.  -because, project-synthesis cannot “see” inside IP that underwent OOC synthesis. 

If implementation does not throw a warning about a timing constraint, then you can ignore the synthesis warning about the timing constraint.

Also, do you have a reason for using the set_false_path constraint?  “My design does not pass timing analysis”, by itself, is a bad reason.   

However, maybe I can help you with a reason.  In the path that is failing timing, I see the word “coolgate” which I think is part of BRAM power optimization (a circuit that disables BRAM when it is not in use and saves electrical power).  See the following post for some details. 

https://forums.xilinx.com/xlnx/board/crawl_message?board.id=OTHERIP&message.id=3144

Also, as recommend in that post, try using the NoBramPowerOpt directive in Vivado implementation (instead of using set_false_path) to solve your timing analysis problem.  That is, using this directive may help you pass timing analysis by removing the "coolgate" path - but your FPGA might then use a little more power when running.

NoBramPowerOpt.jpg

Cheers,
Mark

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Observer
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Registered: ‎02-21-2019

Re: No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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Hello markg@prosensing.com 


.....

If implementation does not throw a warning about a timing constraint, then you can ignore the synthesis warning about the timing constraint.

Also, do you have a reason for using the set_false_path constraint?  “My design does not pass timing analysis”, by itself, is a bad reason.   


 Thank you for help, I will try your suggestions with options  you highlighted.

Reason for false path : it's a path from a user switch on the board, and there is no reason it should be anywhere within nanoseconds.  (I'm just switching it on, off manually).

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Re: No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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@hemangd 

Oh I saw those emails and I didn't understand what /why there are ... Ok, I'm on it .

Will report

EDIT:  Says , you were sent a "test package", but when I login there is nothing to download, no any Test Package anywhere.. Do I understand it wrong? Am I just suppose to reply within that system / account you created?

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Re: No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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markg@prosensing.com 

Yes, that  NoBramPowerOpt is/was the cause of that path.

Subsequently, adding that option to the Project Implementation removed that path entirely  - that is, Path 49 (which was the problematic one) is now something else / that path removed.
My XDC constraint is flagged as non-existent at Implementation too - so yea.

So for now it's definitely works for removing that one timing failure (it wasn't  a problem as such, system would work just fine, but that path shouldn't be there at all, as I see). Now, next step sometime is to understand why it would have been inserted there to begin with    But I need some time on it.

Is it Ok with you if I mark your reply as Solution / Resolution (or answer) ? 

EDIT: I'm just wondering, isn't better to ask Vivado to ignore that timing failure  (which is  < 1ns, definitely not care for that path), rather than disabling power optimization?  
If I cannot use set_false_path here, anything else I can set to make it pass the timing tests / ignore that specific path? (  but keep power optimization on).   I know i can just ignore the failed timing error and generate the bit file and program & use FPGA, but would be nice to not get the error trace

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Registered: ‎01-22-2015

Re: No valid object found for constraint spec/command copied directly from Vivado after Implementation results

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@hemangd  :  I’m sorry for jumping in on this post.  However, I saw an opportunity to talk about BRAM power optimization, which has been a pet-peeve of mine.

 

@dry  :   I’m glad that the NoBramPowerOpt directive helped solve the problem.

BRAM power optimization is not described in detail by the Xilinx literature.  However, by observing Vivado implementation results, I understand that BRAM power optimization works as follows.

You’ll recall that BRAM has inputs called ENA and ENB which you can use to enable/disable parts of the BRAM.  When BRAM power optimization is ON then it adds circuits to whatever control you use for ENA and ENB.  These added circuits attempt to guess when the BRAM is not being used.  When these added circuits think the BRAM is not being used then they disable the BRAM by setting ENA and ENB low.  However, as you saw, these added circuits can sometimes cause timing analysis problems.  Also, in older versions of Vivado, the NoBramPowerOpt directive was not working (ie. you were unable to turn OFF the BRAM power optimization).

Normally, we control ENA and ENB with our HDL.  That is, we create our own BRAM power optimization (ie. setting ENA and ENB low when not using BRAM).  So, to ensure that ENA and ENB are working in a timely manner, it is important that we do NOT use set_false_path on the signal paths to ENA and ENB.

You are probably wondering how much power is being saved by BRAM power optimization.  To answer this question, I show below the Vivado report_power graph for a Kintex-7 project where I am using over 95% of the device's BRAM.  Note that BRAM power consumption is estimated to be about 12% (0.183W) of the total power budget for the project.
Kintex7_report_power.jpg

Cheers,
Mark