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Explorer
684 Views
Registered: ‎01-15-2019

## Number of Logic Levels -> Timing Closure

Hi All,

Is there a thumb rule, which would say how many logic levels are allowed for a certain clock frequency?

For example, for Zynq 7045, for a clock frequency of 156MHz, how many Logic Levels are allowed?

I need this number in order to know how to write/structure my RTL code.

For example, some of my logic with 30 Logic Levels meets the timing requirements and other logic with 15 Logic Levels doesn't meet it (due to the route)...

So, what's the rule for writing a timing-friendly RTL? How many Logic Levels are allowed for a certain frequency (any formula)?

Thank you!

16 Replies
Teacher
676 Views
Registered: ‎07-09-2009

## Re: Number of Logic Levels -> Timing Closure

there is no rule,
as chips improve over years, and the frequency needed goes up, the target keeps moving,

basic thing to remember is that FPGAs are register rich,
and the tools are very good at moving registers around to meet timing,

Explorer
675 Views
Registered: ‎01-15-2019

## Re: Number of Logic Levels -> Timing Closure

So, why in my design a logic with 30 Logic Levels meets the timing requirements and other logic with 15 Logic Levels doesn't meet it (due to the route, which takes ~75% of the path delay)?

How to solve so long trip of the route (without the pblock)?

Teacher
667 Views
Registered: ‎07-09-2009

## Re: Number of Logic Levels -> Timing Closure

but my guess is

a) the paths are not constrained,
or
b) the logic levels get optimised by the tools,

How are you measuring the logic delays ?
rtl / pre or post synthesis,

Explorer
666 Views
Registered: ‎01-15-2019

## Re: Number of Logic Levels -> Timing Closure

"How are you measuring the logic delays?" - by the post P&R timing_report command

Teacher
663 Views
Registered: ‎07-09-2009

## Re: Number of Logic Levels -> Timing Closure

can we see the output please
Explorer
661 Views
Registered: ‎01-15-2019

## Re: Number of Logic Levels -> Timing Closure

```Slack (VIOLATED) :        -0.768ns  (required time - arrival time)
Source:                 i_pl/i_xgs_txmac_top/fs_builder_inst/fs_build_alloc_id_reg[4]/C
(rising edge-triggered cell FDRE clocked by clk_156M25_mmcm  {rise@0.000ns fall@3.200ns period=6.400ns})
Destination:            i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder_reg[4]/D
(rising edge-triggered cell FDRE clocked by clk_156M25_mmcm  {rise@0.000ns fall@3.200ns period=6.400ns})
Path Group:             clk_156M25_mmcm
Path Type:              Setup (Max at Slow Process Corner)
Requirement:            6.400ns  (clk_156M25_mmcm rise@6.400ns - clk_156M25_mmcm rise@0.000ns)
Data Path Delay:        6.948ns  (logic 1.899ns (27.332%)  route 5.049ns (72.668%))
Logic Levels:           18  (CARRY4=5 LUT2=1 LUT6=12)
Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD):    -3.040ns = ( 3.360 - 6.400 )
Source Clock Delay      (SCD):    -3.633ns
Clock Pessimism Removal (CPR):    -0.738ns
Clock Uncertainty:      0.118ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter     (TSJ):    0.071ns
Discrete Jitter          (DJ):    0.224ns
Phase Error              (PE):    0.000ns

Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
-------------------------------------------------------------------    -------------------
(clock clk_156M25_mmcm rise edge)
0.000     0.000 r
W23                  IBUF                         0.000     0.000 r  i_pl/i_pmu/i_bufg/i_clk1_25mhz_bufg/O
net (fo=2, unplaced)         0.584     0.584    i_pl/i_pmu/i_mmcm/inst/clk_in1
net (fo=1, unplaced)         0.419    -4.310    i_pl/i_pmu/i_mmcm/inst/clk_156M25_mmcm
r  i_pl/i_pmu/i_mmcm/inst/clkout1_buf/I
BUFG (Prop_bufg_I_O)         0.093    -4.217 r  i_pl/i_pmu/i_mmcm/inst/clkout1_buf/O
net (fo=58472, unplaced)     0.584    -3.633    i_pl/i_xgs_txmac_top/fs_builder_inst/clk_156M25
FDRE                                         r  i_pl/i_xgs_txmac_top/fs_builder_inst/fs_build_alloc_id_reg[4]/C
-------------------------------------------------------------------    -------------------
FDRE (Prop_fdre_C_Q)         0.233    -3.400 r  i_pl/i_xgs_txmac_top/fs_builder_inst/fs_build_alloc_id_reg[4]/Q
net (fo=65, unplaced)        0.616    -2.784    i_pl/i_xgs_txmac_top/fs_builder_inst/fs_build_alloc_id[4]
r  i_pl/i_xgs_txmac_top/fs_builder_inst/i___3_i_9__46/I0
LUT6 (Prop_lut6_I0_O)        0.123    -2.661 r  i_pl/i_xgs_txmac_top/fs_builder_inst/i___3_i_9__46/O
net (fo=1, unplaced)         0.000    -2.661    i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___0/i___3_i_1_0[1]
r  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___0/i___3_i_3/S[1]
CARRY4 (Prop_carry4_S[1]_CO[3])
0.256    -2.405 r  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___0/i___3_i_3/CO[3]
net (fo=1, unplaced)         0.007    -2.398    i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___0/i___3_i_3_n_1
r  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___0/i___3_i_1/CI
CARRY4 (Prop_carry4_CI_CO[0])
0.147    -2.251 f  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___0/i___3_i_1/CO[0]
net (fo=17, unplaced)        0.247    -2.004    i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___0/CO[0]
f  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___0/status_report_d13_reg[21]_srl13___i_xgs_txmac_top_fs_builder_inst_flush_done_dx_reg_r_16_i_46/I1
LUT2 (Prop_lut2_I1_O)        0.128    -1.876 f  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___0/status_report_d13_reg[21]_srl13___i_xgs_txmac_top_fs_builder_inst_flush_done_dx_reg_r_16_i_46/O
net (fo=53, unplaced)        0.623    -1.253    i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___1/hit_on_alloc[51]_792
f  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___1/status_report_d13_reg[21]_srl13___i_xgs_txmac_top_fs_builder_inst_flush_done_dx_reg_r_16_i_39/I1
LUT6 (Prop_lut6_I1_O)        0.043    -1.210 f  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___1/status_report_d13_reg[21]_srl13___i_xgs_txmac_top_fs_builder_inst_flush_done_dx_reg_r_16_i_39/O
net (fo=1, unplaced)         0.532    -0.678    i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___1/status_report_d13_reg[21]_srl13___i_xgs_txmac_top_fs_builder_inst_flush_done_dx_reg_r_16_i_39_n_1
f  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___1/status_report_d13_reg[21]_srl13___i_xgs_txmac_top_fs_builder_inst_flush_done_dx_reg_r_16_i_11/I0
LUT6 (Prop_lut6_I0_O)        0.043    -0.635 r  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[17].alloc_id___1/status_report_d13_reg[21]_srl13___i_xgs_txmac_top_fs_builder_inst_flush_done_dx_reg_r_16_i_11/O
net (fo=103, unplaced)       0.370    -0.265    i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[16].alloc_id___0/status_report_d13_reg[19]_srl13___i_xgs_txmac_top_fs_builder_inst_flush_done_dx_reg_r_16_i_11_1
r  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[16].alloc_id___0/pli_d2[3]_i_21/I5
LUT6 (Prop_lut6_I5_O)        0.043    -0.222 r  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[16].alloc_id___0/pli_d2[3]_i_21/O
net (fo=1, unplaced)         0.242     0.020    i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[16].alloc_id___0/pli_d2[3]_i_21_n_1
r  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[16].alloc_id___0/pli_d2[3]_i_12/I0
LUT6 (Prop_lut6_I0_O)        0.043     0.063 f  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[16].alloc_id___0/pli_d2[3]_i_12/O
net (fo=1, unplaced)         0.270     0.333    i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[8].alloc_id___0/xgem_reminder[3]_i_18_2
f  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[8].alloc_id___0/pli_d2[3]_i_4/I5
LUT6 (Prop_lut6_I5_O)        0.043     0.376 r  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[8].alloc_id___0/pli_d2[3]_i_4/O
net (fo=2, unplaced)         0.281     0.657    i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[21].alloc_id___0/pli_d2_reg[3]_0
r  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[21].alloc_id___0/pli_d2[3]_i_2/I5
LUT6 (Prop_lut6_I5_O)        0.043     0.700 r  i_pl/i_xgs_txmac_top/enet_xgs_tx_if_inst/generate_block_identifier[21].alloc_id___0/pli_d2[3]_i_2/O
net (fo=9, unplaced)         0.311     1.011    i_pl/i_xgs_txmac_top/fs_builder_inst/fs_build_packet_reminder_alloc_x[1]
r  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[11]_i_159/I2
LUT6 (Prop_lut6_I2_O)        0.043     1.054 r  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[11]_i_159/O
net (fo=1, unplaced)         0.294     1.348    i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[11]_i_159_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder_reg[11]_i_90/DI[1]
CARRY4 (Prop_carry4_DI[1]_CO[3])
0.253     1.601 r  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder_reg[11]_i_90/CO[3]
net (fo=1, unplaced)         0.007     1.608    i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder_reg[11]_i_90_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder_reg[11]_i_35/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.054     1.662 r  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder_reg[11]_i_35/CO[3]
net (fo=1, unplaced)         0.000     1.662    i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder_reg[11]_i_35_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder_reg[11]_i_14/CI
CARRY4 (Prop_carry4_CI_CO[0])
0.147     1.809 f  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder_reg[11]_i_14/CO[0]
net (fo=7, unplaced)         0.302     2.111    i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder2
f  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[4]_i_12/I3
LUT6 (Prop_lut6_I3_O)        0.128     2.239 f  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[4]_i_12/O
net (fo=1, unplaced)         0.407     2.646    i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[4]_i_12_n_1
f  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[4]_i_5/I0
LUT6 (Prop_lut6_I0_O)        0.043     2.689 f  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[4]_i_5/O
net (fo=1, unplaced)         0.270     2.959    i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[4]_i_5_n_1
f  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[4]_i_2/I0
LUT6 (Prop_lut6_I0_O)        0.043     3.002 r  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[4]_i_2/O
net (fo=1, unplaced)         0.270     3.272    i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[4]_i_2_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[4]_i_1/I3
LUT6 (Prop_lut6_I3_O)        0.043     3.315 r  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[4]_i_1/O
net (fo=1, unplaced)         0.000     3.315    i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder[4]_i_1_n_1
FDRE                                         r  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder_reg[4]/D
-------------------------------------------------------------------    -------------------

(clock clk_156M25_mmcm rise edge)
6.400     6.400 r
W23                  IBUF                         0.000     6.400 r  i_pl/i_pmu/i_bufg/i_clk1_25mhz_bufg/O
net (fo=2, unplaced)         0.439     6.839    i_pl/i_pmu/i_mmcm/inst/clk_in1
net (fo=1, unplaced)         0.398     2.838    i_pl/i_pmu/i_mmcm/inst/clk_156M25_mmcm
r  i_pl/i_pmu/i_mmcm/inst/clkout1_buf/I
BUFG (Prop_bufg_I_O)         0.083     2.921 r  i_pl/i_pmu/i_mmcm/inst/clkout1_buf/O
net (fo=58472, unplaced)     0.439     3.360    i_pl/i_xgs_txmac_top/fs_builder_inst/clk_156M25
FDRE                                         r  i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder_reg[4]/C
clock pessimism             -0.738     2.622
clock uncertainty           -0.118     2.504
FDRE (Setup_fdre_C_D)        0.043     2.547    i_pl/i_xgs_txmac_top/fs_builder_inst/xgem_reminder_reg[4]
-------------------------------------------------------------------
required time                          2.547
arrival time                          -3.315
-------------------------------------------------------------------
slack                                 -0.768    ```
Teacher
615 Views
Registered: ‎07-09-2009

## Re: Number of Logic Levels -> Timing Closure

Yep, a long path fails,
you say you have another that pass's ,
can we see that ?

Looks like you have a long carry chain there
Xilinx Employee
582 Views
Registered: ‎07-16-2008

## 回复： Number of Logic Levels -> Timing Closure

I think for Zynq device family, 15~16 logic levels are upper limit for 156MHz frequency, provided that the placement is ideal (without routing congestion etc).

You need to optimize the RTL to reduce logic levels to guarantee timing.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Explorer
573 Views
Registered: ‎01-15-2019

## 回复： Number of Logic Levels -> Timing Closure

How can I report conjections (global)?

How can I report conjections related to a certain path (or see this in a timing report)?

Explorer
570 Views
Registered: ‎01-15-2019

## 回复： Number of Logic Levels -> Timing Closure

Here is a timing report of the path with 24 Logic Levels (CARRY4=18), in the same design as a previous path report and on the same run:

```Slack (MET) :             1.011ns  (required time - arrival time)
Source:                 i_pl/i_xgs_txmac_top/fs_builder_inst/tx_ifc_reg[2]/C
(rising edge-triggered cell FDRE clocked by clk_156M25_mmcm  {rise@0.000ns fall@3.200ns period=6.400ns})
Destination:            i_pl/i_xgs_txmac_top/fs_builder_inst/busy_reg/D
(rising edge-triggered cell FDRE clocked by clk_156M25_mmcm  {rise@0.000ns fall@3.200ns period=6.400ns})
Path Group:             clk_156M25_mmcm
Path Type:              Setup (Max at Slow Process Corner)
Requirement:            6.400ns  (clk_156M25_mmcm rise@6.400ns - clk_156M25_mmcm rise@0.000ns)
Data Path Delay:        5.169ns  (logic 2.700ns (52.234%)  route 2.469ns (47.766%))
Logic Levels:           24  (CARRY4=18 LUT2=2 LUT5=1 LUT6=3)
Clock Path Skew:        -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD):    -3.040ns = ( 3.360 - 6.400 )
Source Clock Delay      (SCD):    -3.633ns
Clock Pessimism Removal (CPR):    -0.738ns
Clock Uncertainty:      0.118ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter     (TSJ):    0.071ns
Discrete Jitter          (DJ):    0.224ns
Phase Error              (PE):    0.000ns

Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
-------------------------------------------------------------------    -------------------
(clock clk_156M25_mmcm rise edge)
0.000     0.000 r
W23                  IBUF                         0.000     0.000 r  i_pl/i_pmu/i_bufg/i_clk1_25mhz_bufg/O
net (fo=2, unplaced)         0.584     0.584    i_pl/i_pmu/i_mmcm/inst/clk_in1
net (fo=1, unplaced)         0.419    -4.310    i_pl/i_pmu/i_mmcm/inst/clk_156M25_mmcm
r  i_pl/i_pmu/i_mmcm/inst/clkout1_buf/I
BUFG (Prop_bufg_I_O)         0.093    -4.217 r  i_pl/i_pmu/i_mmcm/inst/clkout1_buf/O
net (fo=58472, unplaced)     0.584    -3.633    i_pl/i_xgs_txmac_top/fs_builder_inst/clk_156M25
FDRE                                         r  i_pl/i_xgs_txmac_top/fs_builder_inst/tx_ifc_reg[2]/C
-------------------------------------------------------------------    -------------------
FDRE (Prop_fdre_C_Q)         0.233    -3.400 r  i_pl/i_xgs_txmac_top/fs_builder_inst/tx_ifc_reg[2]/Q
net (fo=8, unplaced)         0.305    -3.095    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/Q[1]
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_i_191/I0
LUT2 (Prop_lut2_I0_O)        0.123    -2.972 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_i_191/O
net (fo=1, unplaced)         0.000    -2.972    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_i_191_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_125/S[1]
CARRY4 (Prop_carry4_S[1]_CO[3])
0.256    -2.716 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_125/CO[3]
net (fo=1, unplaced)         0.007    -2.709    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_125_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_76/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.054    -2.655 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_76/CO[3]
net (fo=32, unplaced)        0.496    -2.159    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/CO[0]
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_i_266/I0
LUT2 (Prop_lut2_I0_O)        0.043    -2.116 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_i_266/O
net (fo=1, unplaced)         0.000    -2.116    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_i_266_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_249/S[1]
CARRY4 (Prop_carry4_S[1]_CO[3])
0.256    -1.860 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_249/CO[3]
net (fo=1, unplaced)         0.007    -1.853    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_249_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_255/CI
CARRY4 (Prop_carry4_CI_O[0])
0.114    -1.739 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_255/O[0]
net (fo=2, unplaced)         0.476    -1.263    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/start_burst_sfc[4]
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_248/S[3]
CARRY4 (Prop_carry4_S[3]_CO[3])
0.303    -0.960 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_248/CO[3]
net (fo=1, unplaced)         0.007    -0.953    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_248_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_247/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.054    -0.899 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_247/CO[3]
net (fo=1, unplaced)         0.000    -0.899    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_247_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_225/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.054    -0.845 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_225/CO[3]
net (fo=1, unplaced)         0.000    -0.845    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_225_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_224/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.054    -0.791 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_224/CO[3]
net (fo=1, unplaced)         0.000    -0.791    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_224_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_223/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.054    -0.737 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_223/CO[3]
net (fo=1, unplaced)         0.000    -0.737    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_223_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_176/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.054    -0.683 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_176/CO[3]
net (fo=1, unplaced)         0.000    -0.683    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_176_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_175/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.054    -0.629 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_175/CO[3]
net (fo=1, unplaced)         0.000    -0.629    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_175_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_174/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.054    -0.575 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_174/CO[3]
net (fo=1, unplaced)         0.000    -0.575    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_174_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_113/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.054    -0.521 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_113/CO[3]
net (fo=1, unplaced)         0.000    -0.521    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_113_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_112/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.054    -0.467 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_112/CO[3]
net (fo=1, unplaced)         0.000    -0.467    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_112_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_111/CI
CARRY4 (Prop_carry4_CI_CO[3])
0.054    -0.413 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_111/CO[3]
net (fo=1, unplaced)         0.000    -0.413    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_111_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_65/CI
CARRY4 (Prop_carry4_CI_O[0])
0.114    -0.299 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_i_65/O[0]
net (fo=1, unplaced)         0.416     0.117    i_pl/i_xgs_txmac_top/bw_map_fifo_inst/ifc_in_range_return20_in[44]
r  i_pl/i_xgs_txmac_top/bw_map_fifo_inst/fs_builder_executes_burst_i_61/I0
LUT6 (Prop_lut6_I0_O)        0.123     0.240 r  i_pl/i_xgs_txmac_top/bw_map_fifo_inst/fs_builder_executes_burst_i_61/O
net (fo=1, unplaced)         0.000     0.240    i_pl/i_xgs_txmac_top/bw_map_fifo_inst/fs_builder_executes_burst_i_61_n_1
r  i_pl/i_xgs_txmac_top/bw_map_fifo_inst/fs_builder_executes_burst_reg_i_27/S[3]
CARRY4 (Prop_carry4_S[3]_CO[3])
0.180     0.420 r  i_pl/i_xgs_txmac_top/bw_map_fifo_inst/fs_builder_executes_burst_reg_i_27/CO[3]
net (fo=1, unplaced)         0.000     0.420    i_pl/i_xgs_txmac_top/bw_map_fifo_inst/fs_builder_executes_burst_reg_i_27_n_1
r  i_pl/i_xgs_txmac_top/bw_map_fifo_inst/fs_builder_executes_burst_reg_i_11/CI
CARRY4 (Prop_carry4_CI_CO[0])
0.147     0.567 f  i_pl/i_xgs_txmac_top/bw_map_fifo_inst/fs_builder_executes_burst_reg_i_11/CO[0]
net (fo=1, unplaced)         0.191     0.758    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_reg_6[0]
f  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_i_4/I3
LUT6 (Prop_lut6_I3_O)        0.128     0.886 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_i_4/O
net (fo=1, unplaced)         0.270     1.156    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_i_4_n_1
r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_i_1/I3
LUT5 (Prop_lut5_I3_O)        0.043     1.199 f  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/fs_builder_executes_burst_i_1/O
net (fo=4, unplaced)         0.294     1.493    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/start_burst_p1
f  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/busy_i_1__0/I1
LUT6 (Prop_lut6_I1_O)        0.043     1.536 r  i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst/busy_i_1__0/O
net (fo=1, unplaced)         0.000     1.536    i_pl/i_xgs_txmac_top/fs_builder_inst/sfc_calc_start_burst_n_28
FDRE                                         r  i_pl/i_xgs_txmac_top/fs_builder_inst/busy_reg/D
-------------------------------------------------------------------    -------------------

(clock clk_156M25_mmcm rise edge)
6.400     6.400 r
W23                  IBUF                         0.000     6.400 r  i_pl/i_pmu/i_bufg/i_clk1_25mhz_bufg/O
net (fo=2, unplaced)         0.439     6.839    i_pl/i_pmu/i_mmcm/inst/clk_in1
net (fo=1, unplaced)         0.398     2.838    i_pl/i_pmu/i_mmcm/inst/clk_156M25_mmcm
r  i_pl/i_pmu/i_mmcm/inst/clkout1_buf/I
BUFG (Prop_bufg_I_O)         0.083     2.921 r  i_pl/i_pmu/i_mmcm/inst/clkout1_buf/O
net (fo=58472, unplaced)     0.439     3.360    i_pl/i_xgs_txmac_top/fs_builder_inst/clk_156M25
FDRE                                         r  i_pl/i_xgs_txmac_top/fs_builder_inst/busy_reg/C
clock pessimism             -0.738     2.622
clock uncertainty           -0.118     2.504
FDRE (Setup_fdre_C_D)        0.043     2.547    i_pl/i_xgs_txmac_top/fs_builder_inst/busy_reg
-------------------------------------------------------------------
required time                          2.547
arrival time                          -1.536
-------------------------------------------------------------------
slack                                  1.011

Slack (MET) :             1.011ns  (required time - arrival time)```

Moderator
564 Views
Registered: ‎01-16-2013

## 回复： Number of Logic Levels -> Timing Closure

Hi,

To get the congestion level details use report_design_analysis command.

Thanks,
Yash

Teacher
562 Views
Registered: ‎07-09-2009

## 回复： Number of Logic Levels -> Timing Closure

the difference seems to be mainly in the MMCME2_ADV

are you putting one lot of signals in form one side of the chip, and the others form the other side of th echip,

could you add extra register in and out all the signals  ?

Explorer
552 Views
Registered: ‎01-15-2019

## 回复： Number of Logic Levels -> Timing Closure

"the difference seems to be mainly in the MMCME2_ADV" - how did you discovered this? The paths are actually driven by the same clock source (the same MMCM output).

"are you putting one lot of signals in form one side of the chip, and the others form the other side of th echip" - how did you discovered this?

"could you add extra register in and out all the signals?" - sure, but firstly I'd like to understend how this happened (all that you described)

Explorer
544 Views
Registered: ‎01-15-2019

## Re: Number of Logic Levels -> Timing Closure

drjohnsmith wrote: "Looks like you have a long carry chain there" - related to the first path.

So, how did you figured out that there are long carry chains? As for the Logic Levels, they are reported as Logic Levels: 18 (CARRY4=5 LUT2=1 LUT6=12)

Teacher
531 Views
Registered: ‎07-09-2009

## Re: Number of Logic Levels -> Timing Closure

Whats your experinace of this sort of thing ?

Placment, the tools try to place your design, to meet timing,

if they can great, they stop, if they can get real "knickers in a a twist",

The best way I know to cracking th enut, is to not desing for deep / wide logic levels.

Remeber the basic block of the FPGA is a Look Up Table, of a given input width.

There are different speed paths betwene different pats of the logic,

there are things like fast ripple carry routes, fast mux routes, routes that jump LUTs .

e.g.

https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf

https://www.xilinx.com/support/documentation/application_notes/xapp522-mux-design-techniques.pdf

https://www.xilinx.com/support/documentation/application_notes/xapp466.pdf

in times of old, one could / did place things to do the best routing, but that is just not practical now.

there are many papers on how to do such,

e.g.

http://vixra.org/pdf/1405.0043v1.pdf

But what one finds, is al these tricks get absorbed into the compilers, so your inferance gets better .

So , unless its an academic exercise,   place lots of registers in the desing, pipe line , and you will be happy,

So what are you trying to do, get the deisng to meet timming ?

Xilinx Employee
516 Views
Registered: ‎05-08-2012

## Re: Number of Logic Levels -> Timing Closure

Hi @ldm.eth

With the earlier information supplied, the difference in paths looks to be how many logic levels are due to LUTs compared to carry logic. The carry logic has smaller delays.

Besides addressing any congestion, there are a few options you can try to reduce logic levels.

1. If the logic is contained within an out-of-context OOC run, try setting this to use global synthesis. This will ensure more optimization between boundaries which could reduce logic levels.

2. try retiming during synthesis "-retiming". If the synthesis run is still run OOC, then the OOC synthesis would need to have this option added.

3. Try the resouce sharing option "-resource_sharing on" in synthesis. This allows sharing of arithmetic operators with the intent of lowering utilization.

4. Also, overconstraining the clock driving the destination during synthesis could help reduce logic levels.

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