10-13-2019 11:13 AM - edited 10-13-2019 11:14 AM
I have a custom IP which I'm using in my block design. When I launch the synthesis everything seems to be working as it should, but the implementation always get stuck in "Running route_design". It doesn't throw any errors but it never finishes (I've waited for +9 hours).
While the implementation is being executed, I can access the implementation log, where I found many errors of the type INFO: [Opt 31-131] Removed net: ...
The nets that are being removed are all or nearly all of the nets used in my IP design.
I've checked multiple times my design and my VHDL code and I'm not able to find what is the cause of this issue. Could anyone throw some light on this problem?
Thanks in advance.
10-13-2019 11:49 AM
10-13-2019 07:19 PM
Hi @fnc ,
Please try to apply DONT_TOUCH on your top wrapper in RTL or through XDC and check whether it helpsin completing the implementation. For information on how to use DONT_TOUCH, please check below link page no.49:
10-13-2019 10:32 PM
10-14-2019 02:01 AM
The point I wante dto highlight was , you are not trying to place yor IP , but a design which also contains your IP.
have you tried to simualte the complete design your getting the errors on , not just the IP ?
10-29-2019 09:44 PM
Logic optimization stage removes the loadless cells/nets during sweep stage. Open the synthesized design, search and verify the connection of the net mentioned in INFO message.
Regarding longer runtime during route_design, Can you share the runme.log file present in .runs/impl_1 folder. I believe your design must be congested or have high hold violation which is causing the longer runtime.