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Xilinx Employee
Xilinx Employee
247 Views
Registered: ‎05-08-2012

[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin

I wanted to update the community on a new answer record below that explains how to tracing the connectivity relating to the Opt 31-67 error. This is a common error, and the AR has step by step instructions on finding the source of the connectivity issue. 

https://www.xilinx.com/support/answers/72980.html

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