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Explorer
Explorer
181 Views
Registered: ‎05-14-2017

Opt 31-67 with custom IP with AXI Stream bus

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Hello,

I wrote a small custom AXI4-Strean Master IP (no wizard) with the following I/O ports declarations and register assignments:

module RawToAXIStream
    (           
        input wire data_clk,
        input wire [31:0] data_in,
    
        // AXIS Interface
        input wire clk,
        output wire [31:0] tdata,
        output wire [3:0] tstrb,
        output wire [3:0] tkeep,
        output wire tlast,
        output wire tvalid,
        input wire tready
    );
    
    reg tvalid_reg;
    reg [31:0] tdata_reg;
    reg [3:0] tkeep_reg;
    reg [3:0] tstrb_reg;
    reg tlast_reg;
    
    reg [2:0] state;
    reg data_sent;

    assign tdata = tdata_reg;
    assign tvalid = tvalid_reg;
    assign tlast = tlast_reg;
    assign tkeep = tkeep_reg;
    assign tstrb = tstrb_reg;

    // implementation not shown

endmodule

and I want to interface it with an AXI DMA as shown here:

Screenshot_2019-02-01_18-22-33.png

However, on validating the design, Vivado claims that S_AXIS_S2MM interface is not connected:

 [xilinx.com:ip:axi_dma:7.1-11] /axi_dma_0
 ####################################
  S_AXIS_S2MM interface is unconnected
 ####################################

in fact the implementation fails with this error:

[Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: design_1_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_m_valid_dup_i_1__1.

The same happens if I try to connect my IP to a AXI4-Stream Data FIFO as shown here:Screenshot_2019-02-01_18-29-25.png

[Opt 31-67] Problem: A LUT4 cell in the design is missing a connection on input pin I3, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: design_1_i/axis_data_fifo_0/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/count_value_i[3]_i_2.

It seems that Vivado does not recognize the connection between my custom Master IP and the slave.

Do the port must be declared differently to match the connections if it's done without a wizard ?

What am I missing ?

Thanks & Regards,

simozz

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1 Solution

Accepted Solutions
Moderator
Moderator
85 Views
Registered: ‎01-16-2013

Re: Opt 31-67 with custom IP with AXI Stream bus

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@simozz

 

Check "common design errors" in below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug904-vivado-implementation.pdf#page=52

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
4 Replies
Xilinx Employee
Xilinx Employee
141 Views
Registered: ‎05-08-2012

Re: Opt 31-67 with custom IP with AXI Stream bus

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Hi @simozz.

The messaging would indicate that there is a connectivty problem with the LUT in question. I would suggest opening the synthesized design, and following the I1 pin from the message. What is driving this? If undriven, then this should be connected. I will list a good resource for debugging opt_design issues.

https://www.xilinx.com/support/answers/58616.html


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Explorer
Explorer
122 Views
Registered: ‎05-14-2017

Re: Opt 31-67 with custom IP with AXI Stream bus

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Hi @marcb,

What is the main cause of this problem and how to prevent it ?

Regards,

simozz

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Moderator
Moderator
86 Views
Registered: ‎01-16-2013

Re: Opt 31-67 with custom IP with AXI Stream bus

Jump to solution

@simozz

 

Check "common design errors" in below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug904-vivado-implementation.pdf#page=52

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
Explorer
Explorer
75 Views
Registered: ‎05-14-2017

Re: Opt 31-67 with custom IP with AXI Stream bus

Jump to solution

Hello @syedz

That links seems to be more useful.

In fact, initializing the registers into the initial block solved the problem.

Thanks.

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