03-10-2017 04:04 AM
Vivado 2016.4, Windows
There is my architecture "norm" with Multiplier 12.0 core (not Out-Of-Context). There is its instantiation:
norm_i : norm_mult port map ( clk => clk, a => shr_iv, b => sq_vl, p => norm_iv ); norm_q : norm_mult port map ( clk => clk, a => shr_qv, b => sq_vl, p => norm_qv );
I add sub-reference source into IP constructor and pack it into IP. I create another project and add "norm" as IP in Block design. There is "successful" status of "norm" IP in synthesis report. But when I run Implementation there is failure in opt-design stage with this error:
[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'mb_system_i/norm_0/U0/norm_i' of type 'mb_system_i/norm_0/U0/norm_q/norm_mult' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
What is the actual cause of this failure? How can I fix it?
03-10-2017 04:44 AM
Is it possible for you to share the design? If yes, then I will send you a private message where you can upload this design.