I am working with Vivado 2018.2 and using JESD204_PHY and JESD204 block in my block design. I see that the tx output port of my top module do not appear in the implemented design. I did not specify the constraints in the .xdc file. I see in this post https://forums.xilinx.com/t5/Implementation/Leave-top-level-ports-unplaced/m-p/670336/thread-id/14198
that not specifying constraints for a top module port should not be a problem as some package pin is assigned.
I also refered to a similar post to mine which is as follows but that did not help
Can someone suggest what can be done?
Thanks in advance,
Is the output port of the JESD block directly connected to the top level output port?
Do you see package pin constraint for the output port in IP level xdc?