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Adventurer
Adventurer
10,585 Views
Registered: ‎01-10-2014

Output ports are not found when implementing design

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Hello all,

 

I have a strange problem. I'm trying to implement a reference design for Zynq. I attached axi_gpio port to my PS. And now I want to connect it to pins connected to LEDs present on my Zynq Mini-ITX board. I'm copying this part of design from a standard design for my board (Embedded Standalone OS (Bare-Metal) Reference Design ITX) from here:

http://zedboard.org/support/design/2056/17

I'm attaching a screenshot of my connections. 

I have also copied .xdc entries from that design and pasted them to a new .xdc:

 

set_property LOC C6 [ get_ports LEDs_8Bits_tri_o[0]]
set_property IOSTANDARD LVCMOS15 [ get_ports LEDs_8Bits_tri_o[0]]

set_property LOC B6 [ get_ports LEDs_8Bits_tri_o[1]]
set_property IOSTANDARD LVCMOS15 [ get_ports LEDs_8Bits_tri_o[1]]

set_property LOC L9 [ get_ports LEDs_8Bits_tri_o[2]]
set_property IOSTANDARD LVCMOS15 [ get_ports LEDs_8Bits_tri_o[2]]

set_property LOC L10 [ get_ports LEDs_8Bits_tri_o[3]]
set_property IOSTANDARD LVCMOS15 [ get_ports LEDs_8Bits_tri_o[3]]

set_property LOC K10 [ get_ports LEDs_8Bits_tri_o[4]]
set_property IOSTANDARD LVCMOS15 [ get_ports LEDs_8Bits_tri_o[4]]

set_property LOC K11 [ get_ports LEDs_8Bits_tri_o[5]]
set_property IOSTANDARD LVCMOS15 [ get_ports LEDs_8Bits_tri_o[5]]

set_property LOC L12 [ get_ports LEDs_8Bits_tri_o[6]]
set_property IOSTANDARD LVCMOS15 [ get_ports LEDs_8Bits_tri_o[6]]

set_property LOC K12 [ get_ports LEDs_8Bits_tri_o[7]]
set_property IOSTANDARD LVCMOS15 [ get_ports LEDs_8Bits_tri_o[7]]

 

But when synthesising and implementing my design Vivado gives critical warnings on each line of my .xdc:

[Common 17-55] 'set_property' expects at least one object.

What am I doing wrong? 

 

 

Screenshot 2014-10-16 13.26.16.png
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Adventurer
Adventurer
18,310 Views
Registered: ‎01-10-2014
Well, I just had to regenerate HDL wrapper so that my signals could appear is schematics

View solution in original post

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Xilinx Employee
Xilinx Employee
10,574 Views
Registered: ‎02-16-2014

Hi,

 

Can you run get_ports after opening synthesized design and see if you see can this ports in the output?

If you can see the ports compare the port names with the names given in XDC.

If they don't match please corrcet them.

 

Check this related article,http://www.xilinx.com/support/answers/56169.html

 

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Xilinx Employee
Xilinx Employee
10,573 Views
Registered: ‎02-06-2013

Hi

 

 

The names specified in the constraint file and the design are not matching.

 

Correct them.

Regards,

Satish

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Adventurer
Adventurer
10,562 Views
Registered: ‎01-10-2014
I'm running get_ports and I can't even see the ports I've created in my design. But those ports are listed in design hierarchy. I've checked dozens of times - their names match with those listed in .xdc.
I just right-buttoned the GPIO group (on the pic above) and pressed 'Make external'. Is that right?
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Adventurer
Adventurer
18,311 Views
Registered: ‎01-10-2014
Well, I just had to regenerate HDL wrapper so that my signals could appear is schematics

View solution in original post

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