UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer bgelb
Observer
12,454 Views
Registered: ‎01-14-2009

PAR error / bus macro LOC constraints

Jump to solution

I am experimenting with some custom bus macros for a partial reconfiguration design on a Virtex 5 (academic, not production). I have patterned them after the Virtex4 macros - which use one CLB inside the PR region, and one CLB outside.

 

My constraints look like this:

 

INST "tgen" AREA_GROUP = "AG_PRregion1";
AREA_GROUP "AG_PRregion1" RANGE = SLICE_X30Y100:SLICE_X51Y119;
AREA_GROUP "AG_PRregion1" MODE = RECONFIG;

AREA_GROUP "AG_PRregion1" ROUTING = CLOSED;
INST "high4" LOC = SLICE_X28Y100;
INST "low4" LOC = SLICE_X28Y101;
INST "en_macro" LOC = SLICE_X28Y102;

 

The three "INST" lines are bus macros. The AG range starts at X30, the macros are (R-to-L) placed at X28, which makes them straddle the PR region boundary (one CLB inside, one CLB outside).

 

All is well through running map - I get an NCD which has my macros placed where I want them, and ratsnest for all of the unrouted nets.

 

But, when I run it through PAR, I get the following:

 

ERROR: The component named "en_macro/inside" .
       is owned by more than one Area Group constraint. Each
       component may only be owned by one Area Group constraint.
       Please resolve this constraint conflict by modifying the "SLICEL"
       ranges for the following Area Group constraints:
       Area Group named "AG_PRregion1" owns this comp.
       Area Group named "AG_PRregion1" owns this comp.

 

For each macro. For some reason its counting the same AG twice? How can I fix this?

 

Thanks,

Ben

0 Kudos
1 Solution

Accepted Solutions
Observer bgelb
Observer
14,467 Views
Registered: ‎01-14-2009

Re: PAR error / bus macro LOC constraints

Jump to solution

FIXED!

 

I just recreated my custom macros from scratch (originally I had edited the V5 macros). Now it works fine. Pretty mysterious though. I guess there is more information lurking in NMC and NCD files than is actually visible/editable in the FPGA editor.

 

Anyway, I can provide an NMC that breaks the EAPR toolchain, if thats helpful to anybody :).

 

Ben

0 Kudos
11 Replies
Xilinx Employee
Xilinx Employee
12,444 Views
Registered: ‎08-13-2007

Re: PAR error / bus macro LOC constraints

Jump to solution

I've never tried a V5 PR design using the V4 bus macros so I don't personally know what will happen.

There are V5 bus macros available which I would expect you to be using.

busmacro_xc5v_async.nmc
busmacro_xc5v_async_enable.nmc

 

There are also a few example designs for V5 in the PR EA lounge.

 

Note also the V5 has limited support in the current tools (9.2.04PR11). PR is still a pretty niche and support-intensive flow - most customers using it are under direct support from a Xilinx FAE who has agreed to engage on the opportunity. I do understand the academic interest - I'm just not sure how much help you will receive here as a result.

 

bt

0 Kudos
Observer bgelb
Observer
12,435 Views
Registered: ‎01-14-2009

Re: PAR error / bus macro LOC constraints

Jump to solution

Thanks for the quick reply. I do recognize the evolving, bleeding edge nature of the flow (but naturally this is why its an interesting topic of study).

 

I have used the single-slice macros. They do work fine. I am not using the V4 macros (they wouldn't work since the logic resources are different) - but rather I made up some in FPGA editor, that resemble the V4 ones in structure (one slice on each side of the boundary, instead of a single slice).

 

For what I am working on, I really want to be able to control the routing to the bus macro on the PR side of the boundary, which is much more difficult to do with the single-slice design.

 

I am still using PR8, so I will give it a try with PR11, though not expecting any miracles.

 

Still, PAR is spitting out an error message - surely somebody coded the error message, is there not any information pertaining to it? Are there better (perhaps more specific to EAPR) avenues of support available to univeristy students than this one?

 

Thanks,

Ben

Message Edited by bgelb on 01-24-2009 06:28 PM
0 Kudos
Xilinx Employee
Xilinx Employee
12,427 Views
Registered: ‎08-13-2007

Re: PAR error / bus macro LOC constraints

Jump to solution

Ben,

 

Thanks for the clarification. It wasn't initially obvious to me based on your first post that you had already used the standard V5 PR macros - I thought you might be modifying the V4 as a baseline for other reasons (such as the fact they wouldn't work on V5) without the original V5 macros.

 

I couldn't readily find information on the source of the message. I suspect it has something to do with your modified macro, but can't immediately offer any evidence to support that.

 

I have seen a PR mailing list at the University of Queensland, but haven't read it in quite awhile:

http://www.itee.uq.edu.au/~listarch/partial-reconfig/ (partial reconfiguration mailing list archive)

bt

0 Kudos
Observer bgelb
Observer
12,416 Views
Registered: ‎01-14-2009

Re: PAR error / bus macro LOC constraints

Jump to solution

Well I will keep poking around, hopefully figure it out. I will try the list you suggested as well.

 

In the interest of completeness... I get the same errors when I run DRC directly on the post-map NCD file.

 

Also, if I open the post-map NCD file in Floorplanner, I get this error: "The design has area group(s) with more than one range constraint (e.g. AG_PRregion1). So it seems like there are embedded constraints in the NCD file that are screwed up somehow. Not sure how I can edit/view them directly though.

 

Ben

0 Kudos
Observer bgelb
Observer
12,403 Views
Registered: ‎01-14-2009

Re: PAR error / bus macro LOC constraints

Jump to solution

I note that the error message was added in PR7 of the EAPR flow according to the changelog. Is it possible to obtain pre-PR7 EAPR tools, to check for a regression?

 

(as a side note, the non-patched par completes successfully, for whatever this is worth)

 

Ben

0 Kudos
Observer bgelb
Observer
14,468 Views
Registered: ‎01-14-2009

Re: PAR error / bus macro LOC constraints

Jump to solution

FIXED!

 

I just recreated my custom macros from scratch (originally I had edited the V5 macros). Now it works fine. Pretty mysterious though. I guess there is more information lurking in NMC and NCD files than is actually visible/editable in the FPGA editor.

 

Anyway, I can provide an NMC that breaks the EAPR toolchain, if thats helpful to anybody :).

 

Ben

0 Kudos
Participant jalpa_29
Participant
12,377 Views
Registered: ‎10-17-2008

Re: PAR error / bus macro LOC constraints

Jump to solution
hi, i am working on Virtex-5 for partial reconfiguration. can u send me the nmc file for virtex-5.
0 Kudos
Highlighted
Visitor asohangh
Visitor
11,541 Views
Registered: ‎10-13-2008

Re: PAR error / bus macro LOC constraints

Jump to solution

I'm trying to do something similar except using Top to bottom bus macros.  I've set the reference component to the top slice (slice0) and LOC it one clb outside of the PR region as you have.

When I try to run MAP, I get this error:
ERROR:  SLICEL leds_macro_2_0/slice1 is placed in constraint area MODULE AG:
AG_reconfig_leds.
        This logic is not part of the module reconfig_leds located in this area.
        This area has been instructed not to allow external routing.
        The nets associated with this logic will not be routable.
        Please correct this situation.

I only get these errors if I use ROUTING=CLOSED, but disabling that would defeat the purpose of the custom macros in the first place.

 

So I'm just wondering if you did anything special to create these bus macros.  I started from a new project, used the same CLB configuration as the SingleSlice macros, and added the necessary external pins/connections.  Did you autoroute or manually route the wires in the busmacro?

 

Thanks

0 Kudos
Observer bgelb
Observer
11,533 Views
Registered: ‎01-14-2009

Re: PAR error / bus macro LOC constraints

Jump to solution

YES! There is a secret step.

 

You need to run your nmc file through PR_mergedesign.

 

PR_mergedesign <src nmc file> <dst nmc file>

 

 You'll be greeted with this output from the tool:

 

=======================================================
== Convert Macro to Bus Macro for PR Flow.           ==
=======================================================
The process assumes that all routed nets in the design are networks that will be
used to cross the partial reconfiguration area boundaries.  It also assumes that
all logic in the macro definition is bus macro logic.  If either of these
assumptions are not true of this macro then the behavior of the tools will be
unknown with respect to this macro interface.

Hope this helps.

 

Ben

Visitor asohangh
Visitor
4,233 Views
Registered: ‎10-13-2008

Re: PAR error / bus macro LOC constraints

Jump to solution

Ben, you are the man.  That did get teh PRFlow to see my custom macro as a "real" busmacro.  Now I'm seeing new errors such as this one:

 

 ERROR: Slice Macro Net does not cross Region boundary.
       The Network "leds_macro_1_0/net0" does not cross a boundary.
       Networks marked with "IS_BUS_MACRO" should cross a boundary.
       This network is contained within constraint named: "MODULE AG:
AG_reconfig_leds"
       The slice macro "leds_macro_1_0" is incorrectly placed.
       No further errors will be generated for other nets in this macro.
       Please correct this before continuing.

 

I'm pretty sure my constraints are right, so I'll play with my macros to see if I can figure out the issue.

 

Thanks again,

Ali

0 Kudos
Participant ansarkp
Participant
3,541 Views
Registered: ‎03-31-2009

Re: PAR error / bus macro LOC constraints

Jump to solution

i am working on virtex 4 BUS macros for partial reconfiguration. i do have two busmacros in the form of .nmc files each having only seven i/p and 7 o/p ports. my module contains some 156 i/p ports and 129 o/p ports  so i need to instatiate the same component so many times. how can i write my custom bustom bus macro so that i will end up just 2 bus macros(one for i/p side and second for o/p side). is any code available toedit the busmacro please sent to me. my email:  srikanth@cdactvm.in

 

 

thanks in advance

 

regards 

srikanth

0 Kudos