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Visitor
Visitor
4,415 Views
Registered: ‎11-11-2008

Pack:2515 XST kept optimizing my output enable

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I have a bus of tristate buffer output out of a Virtex-6 FPGA.  The output enable is the same for all 8 bits of this bus.

 

My original code:

assign phy0_data_in[7:0]        = dataoe[0] ? datain[7:0] : 8'bz;

 

I tried:

assign phy0_data_in[7:0]        = {8{dataoe[0]}} ? datain[7:0] : 8'bz;

 

but xst optimized the dataoe to be 1 signal outside the IOB.

I tried making a bus for the dataoe and adding a KEEP attribute to it, but still optimized it away.

 

Full warning message:

WARNING:Pack:2515  - The LUT-1 inverter "][419045_11_INV_0" failed to join the
   OLOGIC comp matched to output buffer "phy1_data_in_2_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter ][419045_11_INV_0 drives
   multiple loads.
and it gave this warning for each data it of my bus.

 

I unchecked "Equivalent Register Removal" and it still optimized it away.

 

Any suggestions?

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Instructor
Instructor
5,444 Views
Registered: ‎07-21-2009

Re: Pack:2515 XST kept optimizing my output enable

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This has nothing to do with registers.

 

The output buffer enable signal is asserted (for enable) LOW, not HIGH.  There is no logic in the IOB to invert the dataoe signal, the inversion must be in the FPGA fabric.

 

So here is an alternate implementation which *may* work.

 

(* IOB="TRUE" *)

reg [7:0]  data_in=0;

 

(* IOB="TRUE" *)

reg [7:0]  data_disa=0;

 

assign data_disa_prereg = ~dataoe;  // invert before register

 

always @(posedge clock)

  begin

    data_in <= data_in_prereg;  // this register will be located in the IOB

    data_disa <= {8{data_disa_prereg}}; // this register will be located in the IOB

  end

 

generate   // tri-state output, code copied from Gabor (gszakacs)

genvar i;  // nasty generate block to instantiate 8 tri-state controls for 8 bits

  for (i = 0;i < 8; i = i + 1)
    begin : IO_BUFS
      assign data_disa[i] = phy0_data_in[i] ? 1'bz : datain[i];
    end
endgenerate

 

I haven't tried this, it's a bit brute force, but it should work (or almost work).

 

-- Bob Elkind

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View solution in original post

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3 Replies
Instructor
Instructor
5,445 Views
Registered: ‎07-21-2009

Re: Pack:2515 XST kept optimizing my output enable

Jump to solution

This has nothing to do with registers.

 

The output buffer enable signal is asserted (for enable) LOW, not HIGH.  There is no logic in the IOB to invert the dataoe signal, the inversion must be in the FPGA fabric.

 

So here is an alternate implementation which *may* work.

 

(* IOB="TRUE" *)

reg [7:0]  data_in=0;

 

(* IOB="TRUE" *)

reg [7:0]  data_disa=0;

 

assign data_disa_prereg = ~dataoe;  // invert before register

 

always @(posedge clock)

  begin

    data_in <= data_in_prereg;  // this register will be located in the IOB

    data_disa <= {8{data_disa_prereg}}; // this register will be located in the IOB

  end

 

generate   // tri-state output, code copied from Gabor (gszakacs)

genvar i;  // nasty generate block to instantiate 8 tri-state controls for 8 bits

  for (i = 0;i < 8; i = i + 1)
    begin : IO_BUFS
      assign data_disa[i] = phy0_data_in[i] ? 1'bz : datain[i];
    end
endgenerate

 

I haven't tried this, it's a bit brute force, but it should work (or almost work).

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

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Professor
Professor
4,396 Views
Registered: ‎08-14-2007

Re: Pack:2515 XST kept optimizing my output enable

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I've found that the more recent versions of ISE will automatically replicate the tristate register,

and handle the inversion (similar to register balancing - i.e. the inversion needs to be at the

D side of the flip-flop) for the T register.  It really sounds like the enable function itself is not

coming from a register, but from combinatorial logic that can't be pushed into the IOB.  As long

as the output enable comes directly from a register, then pushing it into the IOB should work.

 

-- Gabor

-- Gabor
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Visitor
Visitor
4,393 Views
Registered: ‎11-11-2008

Re: Pack:2515 XST kept optimizing my output enable

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Hmm. I am using an older version (11.4), but it has been working for all this time, I don't want to upgrade :)

The oe is coming straight from a register, so I'm trying Bob's suggestion right now and replicating it.

Prior to posting, I did try using generate & didn't work.

 

Thanks for the responses!

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