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wenweizha
Contributor
Contributor
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Registered: ‎02-25-2009

Par (V11.4) ignore "lock_pins" constraint and swap LUT pins position of a bus_macro

I'm using bus_macro "busmacro_xc4v_l2r_async_narrow", with contraint "lock_pins = all", however, LUT pins are till swapped by par.

 

The "busmacro_xc4v_l2r_async_narrow" defined that for its slice0~3, both F and G lut should be defined as "D=A1".

 

However, in the ncd generated by par (normal p&r), F and G function of slice0~3 are changed, some become "D=A3" - so LUT pins are swapped!

 

Interestly, if I only do place with par (-r option), no pins are swapped and all functions remain "D=A1".

 

Why "lock_pins = all" does not work here? Why par try to swap pin location that is defined by a hard macro?

 

thanks

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bwade
Scholar
Scholar
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Registered: ‎07-01-2008

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ywu
Xilinx Employee
Xilinx Employee
3,766 Views
Registered: ‎11-28-2007

 

You will also need to use S="TRUE" constraint on the nets going into the LUTs. Take a look at the blog: Don't optimize my LUT please! for more details.

 


@wenweizha wrote:

I'm using bus_macro "busmacro_xc4v_l2r_async_narrow", with contraint "lock_pins = all", however, LUT pins are till swapped by par.

 

The "busmacro_xc4v_l2r_async_narrow" defined that for its slice0~3, both F and G lut should be defined as "D=A1".

 

However, in the ncd generated by par (normal p&r), F and G function of slice0~3 are changed, some become "D=A3" - so LUT pins are swapped!

 

Interestly, if I only do place with par (-r option), no pins are swapped and all functions remain "D=A1".

 

Why "lock_pins = all" does not work here? Why par try to swap pin location that is defined by a hard macro?

 

thanks


 

Cheers,
Jim
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