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Visitor aroutzoman
Visitor
4,129 Views
Registered: ‎01-22-2011

Perfect simulation and synthesis but weird warnings in Implement Design and Generate programming file- Project not working eventually!

   I've designed a project that includs picoblaze and UART and my design which is a ticket vending machine, a block RAM, a component that converts ascii to binary and sends data to picoblaze and a component which is a "bridge" to connect picoblaze with the vending machine. The vending machine is a whole other project which has been tested and implemented on a Spartan3 and works perfectly!! Now with this new project  I wish to load the number of 4 types of tickets from a PC terminal program on the BRAM through UART and the ascii to binary component.  It's not importnant to analyze the project. What you should know is that picoblaze does all the controlling I need and communicates with the bridge, the block RAM and the ascii to binary component

   Anyway, the thing is that  even though the simulation of the project is perfect, just the way I want things to be, eventually the project is not working on the spartan3 device. I get these warnings during the "Implement Design" procedure:

 

 

 Route 455-   "CLK Net:mult1/errorD_not0001 may have excessive skew because .........."

 

and during the "Generate Programming FIle" procedure:


PhysDesignRules:372 - Gated clock. Clock net mult2/ad_not0001 is sourced
   by a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.

 

etc......

 

What should I be aware of in the design for these warning to disappear?

 

Thank you in advance,

Apostolos

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Mentor awillen
Mentor
4,128 Views
Registered: ‎11-29-2007

Re: Perfect simulation and synthesis but weird warnings in Implement Design and Generate programming file- Project not working eventually!

Please don't post the same question more than once. Thank you.



Please google your question before asking it.
If someone answers your question, mark the post with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left).
Xilinx Employee
Xilinx Employee
4,070 Views
Registered: ‎07-01-2008

Re: Perfect simulation and synthesis but weird warnings in Implement Design and Generate programming file- Project not working eventually!

The Route:455 message is just warning you that you have a non-clock pin on a clock net and so may have some clock skew as a result. From the name used it seems that you are driving a clock off chip. You might want to use a clock forwarding technique for this purpose.

 

http://www.xilinx.com/support/answers/35032.htm

http://www.xilinx.com/support/answers/21723.htm

 

The gated clock warning is similar in that it is warning about a clock that is being forced off the dedicated clock routing resources. You can choose to ignore both warnings if there are no timing issues related to the clocks involved.

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