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Observer
Observer
4,478 Views
Registered: ‎04-14-2017

Pin Assignments In Vivado For Block Designs

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Im migrating from ISE to Vivado to program the Artix AC701 board.

Im following https://www.xilinx.com/video/technology/dma-for-pci-express.html to make a block design in Vivado to connect the DMA and MIG blocks and generate a programmable bitstream.

 

In ISE theres usually one UCF for the pin assignments but it seems in vivado each IP generates internal constraint files.

My question is when the bitstream is generated from a block design, will it automatically assign the internal constraint files to the right pins for the development board in the multiple internal constraint files?

 

 

block.jpg

 

Cheers

-P

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Moderator
Moderator
5,861 Views
Registered: ‎09-15-2016

Re: Pin Assignments In Vivado For Block Designs

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Hi @petersanch

 

IP xdc is read before the user xdc if you set  PROCESSING_ORDER property of IP xdc to Early. The option you can select based on your requirement/ scenario. For detail information refer the below link, page 14:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug903-vivado-using-constraints.pdf

 

IP physical constraints should be properly applied to their intended objects pins as long as we are not specifying the same constraints for the object pins in the top level xdc. To verify you can see the IO ports window once you open the implemented design.

 

Regards

Rohit

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Regards
Rohit
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Adventurer
Adventurer
4,464 Views
Registered: ‎11-13-2017

Re: Pin Assignments In Vivado For Block Designs

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Hi,

 

Yes, the tool will utilize the internal IP constraints (which are demo board specific) and assign them to its pins. Naturally the part selected for the project should be the correct demonstration board. You can verify the pin assignments by opening up the implementation and reviewing the I/O assignments and compare them to the constraint files. 

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Moderator
Moderator
5,862 Views
Registered: ‎09-15-2016

Re: Pin Assignments In Vivado For Block Designs

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Hi @petersanch

 

IP xdc is read before the user xdc if you set  PROCESSING_ORDER property of IP xdc to Early. The option you can select based on your requirement/ scenario. For detail information refer the below link, page 14:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug903-vivado-using-constraints.pdf

 

IP physical constraints should be properly applied to their intended objects pins as long as we are not specifying the same constraints for the object pins in the top level xdc. To verify you can see the IO ports window once you open the implemented design.

 

Regards

Rohit

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

 

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

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Observer
Observer
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Registered: ‎04-14-2017

Re: Pin Assignments In Vivado For Block Designs

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Thanks logictable and thakurr.

I'm new to Vivado and dont know where to search for IO ports window under Implementation.

This is what I see under implementation.

implementation.jpg

 

And these are the tabs.

tabs.jpg

Cheers

-P

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Moderator
Moderator
4,430 Views
Registered: ‎09-15-2016

Re: Pin Assignments In Vivado For Block Designs

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Hi @petersanch

 

Once you complete implementation, open implemented design, at bottom you will see I/O ports window as shown below:

iowind.PNG

Regards

Rohit

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Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

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Observer
Observer
4,401 Views
Registered: ‎04-14-2017

Re: Pin Assignments In Vivado For Block Designs

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Hi thakurr.

I changed the layout to I/O Planning then the IO Ports showed. Cheers!

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Moderator
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Registered: ‎09-15-2016

Re: Pin Assignments In Vivado For Block Designs

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Hi @petersanch

 

Please do close the thread by marking the helpful post as accepted solution.This could prove be beneficial for future users for reference.

 

Regards

Rohit

Regards
Rohit
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