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ipg
Visitor
Visitor
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Registered: ‎01-28-2021

Pin Assingments in Example Designs

Hi,

I have got a general question. I opened an auto-generated HDMI example design for the ZCU106 board.

Now my question: Where is the pin location assignment for e.g. the HDMI_TX_DAT_P_OUT* pins defined?

So, where is the definition, that HDMI_TX_DAT_P_OUT[0] is mapped to pin AN6? I could not find it...

Xilinx_ZCU106_Pin_Assignment.PNG

Thanks for clarification!

Best regards,

ipg

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bruce_karaffa
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Registered: ‎06-21-2017

This should be in an xdc file.  Look in your hierarchy   Sources=>Constraints=>constrs_1 and see what is in there.

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ipg
Visitor
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Registered: ‎01-28-2021

Hi, this is where I also assumed the relevant data, but it is not there. There are 3 xdc files:

 

1) AudioGen.xdc

#
# Copyright (c) 2014 Xilinx, Inc.  All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
#
# This file contains the clock domain crossing false paths for the 
# audio generator.
#
# MODIFICATION HISTORY:
#
# Ver   Who Date         Changes
# ----- --- ----------   -----------------------------------------------
# 1.00  hf  2014/10/21   First release
# 1.02  RHe 2014/12/08   Updated constraints for the added clock domain
#                        crossing logic.
# 1.04  RHe 2015/01/15   Added missing constraints AXI lite to AXI streaming
# 1.07  RHe 2015/04/16   Added timing exception for audio drop signal
################################################################################

 

2) hdmi_acr_ctrl.xdc

#
# Copyright (c) 2014 Xilinx, Inc.  All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
#
# This file contains the clock domain crossing false paths for the 
# the audio clock rate regenerator used in the HDMI Audio Clock Regeneration model.
#
# MODIFICATION HISTORY:
#
# Ver   Who Date         Changes
# ----- --- ----------   -----------------------------------------------
# 1.00  RHe 2014/12/09   First release
# 1.02  RHe 2015/04/14   Added timing exception for audio reset
# 1.03  RHe 2015/07/31   Added timing exception for tmds clock ratio indication
################################################################################

set_false_path -from [get_cells -hier -filter {name=~*HDMI_ACR_CTRL_AXI_INST/rEnab_ACR_reg}] \
               -to   [get_cells -hier -filter {name=~*aud_enab_acr_sync_reg[0]}]

set_false_path -from [get_cells -hier -filter {name=~*HDMI_ACR_CTRL_AXI_INST/rACR_Sel_reg}] \
               -to   [get_cells -hier -filter {name=~*aud_acr_sel_sync_reg[0]}]               
set_false_path -from [get_cells -hier -filter {name=~*HDMI_ACR_CTRL_AXI_INST/rTMDSClkRatio_reg}] \
               -to   [get_cells -hier -filter {name=~*aud_tmdsclkratio_sync_reg[0]}]
               
set_false_path -from [get_cells -hier -filter {name=~*PULSE_CLKCROSS_INST/rIn_Toggle_reg}] \
               -to   [get_cells -hier -filter {name=~*PULSE_CLKCROSS_INST/rOut_Sync_reg[0]}]

set_false_path -from [get_cells -hier -filter {name=~*HDMI_ACR_CTRL_AXI_INST/rAud_Reset_reg}] \
               -to   [get_cells -hier -filter {name=~*aud_rst_chain_reg[*]}]
               
# Clock crossing of the N value from the AXI clock to the Audio clock               
set_false_path -from [get_cells -hier -filter {name=~*NVAL_CLKCROSS_INST/rIn_Data_reg[*]}] \
               -to   [get_cells -hier -filter {name=~*NVAL_CLKCROSS_INST/rOut_Data_reg[*]}]

set_false_path -from [get_cells -hier -filter {name=~*NVAL_CLKCROSS_INST/rIn_DValid_reg}] \
               -to   [get_cells -hier -filter {name=~*NVAL_CLKCROSS_INST/rOut_DValid_Sync_reg[0]}]

set_false_path -from [get_cells -hier -filter {name=~*NVAL_CLKCROSS_INST/rOut_ACK_reg}] \
               -to   [get_cells -hier -filter {name=~*NVAL_CLKCROSS_INST/rIn_ACK_Sync_reg[0]}]
               
# Clock crossing of the CTS value from the HDMI clock to the AXI clock               
set_false_path -from [get_cells -hier -filter {name=~*CTS_CLKCROSS_ACLK_INST/rIn_Data_reg[*]}] \
               -to   [get_cells -hier -filter {name=~*CTS_CLKCROSS_ACLK_INST/rOut_Data_reg[*]}]

set_false_path -from [get_cells -hier -filter {name=~*CTS_CLKCROSS_ACLK_INST/rIn_DValid_reg}] \
               -to   [get_cells -hier -filter {name=~*CTS_CLKCROSS_ACLK_INST/rOut_DValid_Sync_reg[0]}]
  
set_false_path -from [get_cells -hier -filter {name=~*CTS_CLKCROSS_ACLK_INST/rOut_ACK_reg}] \
               -to   [get_cells -hier -filter {name=~*CTS_CLKCROSS_ACLK_INST/rIn_ACK_Sync_reg[0]}]  
               
# Clock crossing of the CTS value from the HDMI clock to the Audio clock               
set_false_path -from [get_cells -hier -filter {name=~*CTS_CLKCROSS_AUD_INST/rIn_Data_reg[*]}] \
               -to   [get_cells -hier -filter {name=~*CTS_CLKCROSS_AUD_INST/rOut_Data_reg[*]}]

set_false_path -from [get_cells -hier -filter {name=~*CTS_CLKCROSS_AUD_INST/rIn_DValid_reg}] \
               -to   [get_cells -hier -filter {name=~*CTS_CLKCROSS_AUD_INST/rOut_DValid_Sync_reg[0]}]

set_false_path -from [get_cells -hier -filter {name=~*CTS_CLKCROSS_AUD_INST/rOut_ACK_reg}] \
               -to   [get_cells -hier -filter {name=~*CTS_CLKCROSS_AUD_INST/rIn_ACK_Sync_reg[0]}]               

 

3) hdmi_example_zcu106.xdc

#####
## Constraints for HDMI 2.0 on ZCU106 
## Version 1.0
#####


#####
## Pins
#####

##
## Video Clock SI570
##
#set_property PACKAGE_PIN U10 [get_ports DRU_CLK_IN_clk_p]; # USER_MGT_SI570_CLOCK1_C_P
set_property PACKAGE_PIN W10 [get_ports DRU_CLK_IN_clk_p];
create_clock -name dru_mgt_refclk -period 6.400 [get_ports DRU_CLK_IN_clk_p]

##
## External Reset (CPU_RESET)
##
set_property PACKAGE_PIN G13 [get_ports reset]
set_property IOSTANDARD LVCMOS18 [get_ports reset]

##
## HDMI RX
##
set_property PACKAGE_PIN AC10 [get_ports HDMI_RX_CLK_P_IN]; #revB
create_clock -name rx_mgt_refclk -period 3.367 [get_ports HDMI_RX_CLK_P_IN]

set_property PACKAGE_PIN M10 [get_ports RX_HPD_OUT];
set_property IOSTANDARD LVCMOS33 [get_ports RX_HPD_OUT];

set_property PACKAGE_PIN M9 [get_ports RX_DDC_OUT_scl_io]; #HDMI_RX_SNK_SCL
set_property IOSTANDARD LVCMOS33 [get_ports RX_DDC_OUT_scl_io]; 
set_property PACKAGE_PIN M11 [get_ports RX_DDC_OUT_sda_io]; #HDMI_RX_SNK_SDA
set_property IOSTANDARD LVCMOS33 [get_ports RX_DDC_OUT_sda_io]; 

set_property PACKAGE_PIN G14 [get_ports RX_REFCLK_P_OUT]; # HDMI_REC_CLOCK_C_P
set_property IOSTANDARD LVDS [get_ports RX_REFCLK_P_OUT]; 

set_property PACKAGE_PIN M8 [get_ports RX_DET_IN]; # HDMI_RX_PWR_DET         
set_property IOSTANDARD LVCMOS33 [get_ports RX_DET_IN]

##
## HDMI TX
##
set_property PACKAGE_PIN AD8 [get_ports TX_REFCLK_P_IN]; #HDMI_SI5324_OUT_C_P
create_clock -name tx_mgt_refclk -period 3.367 [get_ports TX_REFCLK_P_IN]

set_property PACKAGE_PIN G21 [get_ports HDMI_TX_CLK_P_OUT] ; #HDMI_TX_LVDS_OUT_P
set_property IOSTANDARD LVDS [get_ports HDMI_TX_CLK_P_OUT]

set_property PACKAGE_PIN N13 [get_ports TX_HPD_IN]; #HDMI_TX_HPD
set_property IOSTANDARD LVCMOS33 [get_ports TX_HPD_IN]

set_property PACKAGE_PIN N8 [get_ports TX_DDC_OUT_scl_io]; #HDMI_TX_SRC_SCL     
set_property IOSTANDARD LVCMOS33 [get_ports TX_DDC_OUT_scl_io]
set_property PACKAGE_PIN N9 [get_ports TX_DDC_OUT_sda_io]; #HDMI_TX_SRC_SDA       
set_property IOSTANDARD LVCMOS33 [get_ports TX_DDC_OUT_sda_io]


##
## HDMI TX
##
set_property PACKAGE_PIN N12 [get_ports fmch_iic_scl_io]; #HDMI_CTL_SCL      
set_property IOSTANDARD LVCMOS33 [get_ports fmch_iic_scl_io]
set_property PACKAGE_PIN P12 [get_ports fmch_iic_sda_io]; #HDMI_CTL_SDA          
set_property IOSTANDARD LVCMOS33 [get_ports fmch_iic_sda_io]

##
## Misc
##
#GPIO_LED_0_LS
set_property PACKAGE_PIN AL11 [get_ports {LED0}]           
#Only LED 0 is used at the moment     
##GPIO_LED_1_LS
#set_property PACKAGE_PIN AL13 [get_ports {LED1}]           
##GPIO_LED_2_LS
#set_property PACKAGE_PIN AK13 [get_ports {LED2}]           
##GPIO_LED_3_LS
#set_property PACKAGE_PIN AE15 [get_ports {LED3}]           
##GPIO_LED_4_LS
#set_property PACKAGE_PIN AM8  [get_ports {LED4}]           
##GPIO_LED_5_LS
#set_property PACKAGE_PIN AM9  [get_ports {LED5}]           
##GPIO_LED_6_LS
#set_property PACKAGE_PIN AM10 [get_ports {LED6}]           
##GPIO_LED_7_LS
#set_property PACKAGE_PIN AM11 [get_ports {LED7}]           

set_property IOSTANDARD LVCMOS12 [get_ports {LED0}]
#set_property IOSTANDARD LVCMOS12 [get_ports {LED1}]
#set_property IOSTANDARD LVCMOS12 [get_ports {LED2}]
#set_property IOSTANDARD LVCMOS12 [get_ports {LED3}]
#set_property IOSTANDARD LVCMOS12 [get_ports {LED4}]
#set_property IOSTANDARD LVCMOS12 [get_ports {LED5}]
#set_property IOSTANDARD LVCMOS12 [get_ports {LED6}]
#set_property IOSTANDARD LVCMOS12 [get_ports {LED7}]

set_property PACKAGE_PIN H8 [get_ports SI5324_RST_OUT]; #HDMI_SI5324_RST
set_property IOSTANDARD LVCMOS33 [get_ports SI5324_RST_OUT]

set_property PACKAGE_PIN G8 [get_ports SI5324_LOL_IN]; #HDMI_SI5324_LOL
set_property IOSTANDARD LVCMOS33 [get_ports SI5324_LOL_IN]

set_property PACKAGE_PIN N11 [get_ports TX_EN_OUT]; #HDMI_TX_EN
set_property IOSTANDARD LVCMOS33 [get_ports TX_EN_OUT]

#####
## End
#####cd ..



#set_property PACKAGE_PIN E4 [get_ports {HDMI_RX_DAT_P_IN[0]}]
#set_property PACKAGE_PIN D6 [get_ports {HDMI_RX_DAT_P_IN[1]}]   
#set_property PACKAGE_PIN B6 [get_ports {HDMI_RX_DAT_P_IN[2]}]   

##USER_SMA_GPIO_P
#set_property PACKAGE_PIN H27 [get_ports {SMA0}]           
##USER_SMA_GPIO_N
#set_property PACKAGE_PIN G27 [get_ports {SMA1}]           
##USER_SMA_CLOCK_P
#set_property PACKAGE_PIN D23 [get_ports {SMA2}]           
##USER_SMA_CLOCK_N
#set_property PACKAGE_PIN C23 [get_ports {SMA3}]           
#set_property IOSTANDARD LVCMOS33 [get_ports {SMA0}]
#set_property IOSTANDARD LVCMOS33 [get_ports {SMA1}]
#set_property IOSTANDARD LVCMOS33 [get_ports {SMA2}]
#set_property IOSTANDARD LVCMOS33 [get_ports {SMA3}]

#set_property IOSTANDARD LVCMOS18 [get_ports TX_CLKSEL_OUT]
#set_property PACKAGE_PIN E22 [get_ports TX_CLKSEL_OUT]          

#set_property IOSTANDARD LVCMOS18 [get_ports RX_I2C_EN_N_OUT]
#set_property PACKAGE_PIN G24 [get_ports RX_I2C_EN_N_OUT]        

 

But the Pin HDMI_TX_DAT_P_OUT[0] is not mapped here...

 

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