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Explorer
Explorer
3,278 Views
Registered: ‎03-06-2014

Pin to Clock routing warning after implementation

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Dear all,

I am using Vivado2017 targeting a Zedboard including a Zynq-7000 (clg484) FPGA.

I am trying to transmit a signal as a clock between two FPGA Zedboards via FMC connectors. At the Destination board, I take the signal from an N-pin of FMC, and the synthesizer with apply an IBUF for that. Then I instantiated a BUFG in order to consider that signal as a clock to be fed to the flip-flops of my design. The design completely synthesized with no warning or error and also the implementation succeed with no errors, but I receive the following warning in implementation.

Can anyone help me to pass this issue?

 

[DRC PLCK-12] Clock Placer Checks: Poor placement for routing between an IO pin and BUFG. 
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.
This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design.
clksig_IBUF[10]_inst (IBUF.O) is locked to IOB_X1Y63
BUFG_inst11 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y18

 


Kind replies are in advance appreciated.

Regards,

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Adventurer
Adventurer
1,708 Views
Registered: ‎08-30-2018

The reason you get this placing error message is that you have ties your clock signal to a non-clock-capable IO (NCCIO). To solve the problem, do a search on the Git or Xilinx for the package pin of the FPGA type you use. I found it here for you :-) Just tie your cllocksignal to a CCIO pin and let it to place and route. It will solve your problem for sure!

 

Hope I could help

Bests,

Daryon

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Voyager
Voyager
3,262 Views
Registered: ‎06-24-2013

Hey @msdarvishi,

 

There are no dedicated routes to clock buffers for the N-pins.

Also note that not all pins are clock capable, so for the Zedboard you want to use one of the _P_CC pins for single ended clock inputs (CLK1-M2C_P, LA00_P_CC, LA01_P_CC, LA17_P_CC or LA18_P_CC).

 

If you don't care about the clock quality (jitter, routing delay, etc) setting CLOCK_DEDICATED_ROUTE to false is a solution, but it will result in a degraded design.

 

Hope this clarifies,

Herbert

-------------- Yes, I do this for fun!
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Observer
Observer
3,180 Views
Registered: ‎11-21-2013

Hello,

 

Why just not to use IBUFG?

I assume this may help

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Explorer
Explorer
3,165 Views
Registered: ‎03-06-2014

Dear @p.hayk

 

Thanks for your reply. Once I put an IBUFG in my VHDL, after synthesis, it is changed to an IBUF. Then I get the following ERROR since there are an IBUF (not an IBUFG) and a BUFG in series:

 

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clksig_ibufg] >

	IBUFG_inst28 (IBUF.O) is locked to IOB_X1Y119
	 and BUFG_inst28 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

 

Two issues:

1. Why does the synthesizer changes IBUFG to IBUF? (I am using Vivado 2017.1 targetting a Zynq clg484 FPGA)

 

2. Is it possible that IBUFG does not exist anymore in newer generations of FPGAs like Zynqs??

 

I thank in advance for your kind and help.

 

Regards,

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Explorer
Explorer
3,162 Views
Registered: ‎03-06-2014

Dear @p.hayk,

 

As you said, if I only use an IBUFG in my VHDL file, the synthesizer will change it to an IBUF, but after implementation, the following Warning appears rather than the Error message that I have mentioned above:

 

[DRC CKLD-2] Clock Net has IO Driver, not a Clock Buf, and/or non-Clock loads: Clock net clksig_bufg[0] is directly driven by an IO rather than a Clock Buffer or may be an IO driving a mix of Clock Buffer and non-Clock loads. This connectivity should be reviewed and corrected as appropriate. Driver(s): BUFG_inst0/O

 

An issue here: Does this warning message will hurt the design??

 

I am confused between two choices:

 

(1) If I put an IBUFG and then a BUFG in my HDL file, the synthesizer will change IBUFG to an IBUF and gives the Error message shown in my previous post;

 

(2) If I put only an IBUFG in my HDL file, the synthesizer will change IBUFG to an IBUF and gives the Warning message shown above

 

I do not know how to pass this issue?! :(

Thanks and Regards,

 

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Explorer
Explorer
3,151 Views
Registered: ‎03-06-2014

Surprisingly, the IBUFG instantiation in VHDL is translated as IBUFG in Xilinx ISE 14.7 while it is translated to IBUF in Vivado 2017.1 ...!!!! It seems weird and I do not  yet know why...

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Observer
Observer
3,141 Views
Registered: ‎11-21-2013

Hy,

 

I think the issue may be because of pin mapping. I suggest you check to which FPGA pin that clock is connected.

Check if  that pin is general usage or some specific pin of FPGA.

 

Thanks

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Moderator
Moderator
3,107 Views
Registered: ‎05-08-2012

Hi @msdarvishi,

 

Make sure that the package pin in this path is a Clock Capable pin (CCIO). Part of the error should indicated:

 

"This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin"

 

These should be labled SRCC or MRCC when selecting package pins from the package view.

 

 Also, the IBUFG is being phased out, as this is an older primitive. An IBUFG inferring an IBUF is the expected behavior. The BUFG variants should be used instead. 

 

 

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Adventurer
Adventurer
1,709 Views
Registered: ‎08-30-2018

The reason you get this placing error message is that you have ties your clock signal to a non-clock-capable IO (NCCIO). To solve the problem, do a search on the Git or Xilinx for the package pin of the FPGA type you use. I found it here for you :-) Just tie your cllocksignal to a CCIO pin and let it to place and route. It will solve your problem for sure!

 

Hope I could help

Bests,

Daryon

View solution in original post