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Explorer
Explorer
9,350 Views
Registered: ‎05-07-2012

Pipelining DSP48 output will improve performance

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Hello,

 

I'm using the ADDSUB_MACRO in Vivado 2015.1.  I'm getting a lot of warnings that say, 

 

DPOP-1#47 Warning
Output pipelining
DSP sac/sasg[7].sas/cts2/bl.DSP48_2 output P is not pipelined. Pipelining DSP48
output will improve performance. Both multiplier/adder output can be pipelined.
Related violations: <none>

 

My instantiations all look like,

 

cts3: ADDSUB_MACRO
generic map ( DEVICE => "7SERIES",
LATENCY => 2,
WIDTH => 32)
port map ( CARRYOUT => open,
RESULT => totalizersum3,
A => secaccumchadatout3r,
ADD_SUB => '1',
B => asicresultaddend6,
CARRYIN => '0',
CE => '1',
CLK => clock,
RST => sreset);

 

 

So, I'm not understanding why I'm getting pipeline warnings since I'm specifying a latency of 2 which is recommended in the documentation.  I did read an older forum thread that said that this is a bug and would be corrected in version 2014.2.  So, is it still a bug in 2015.1 or am I missing something?

 

Thank you.

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Explorer
Explorer
16,569 Views
Registered: ‎05-07-2012

Re: Pipelining DSP48 output will improve performance

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Thanks.  

 

I just decided to use the IP Catalog and generate a DSP adder core instead of instantiating a primitive.  I'll see how that goes.  

 

 

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Xilinx Employee
Xilinx Employee
9,346 Views
Registered: ‎08-02-2011

Re: Pipelining DSP48 output will improve performance

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Setting it to 2 is perhaps using an input reg and mreg, but no preg. Can you open up the post-synth schematic and see?
www.xilinx.com
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Highlighted
Explorer
Explorer
16,570 Views
Registered: ‎05-07-2012

Re: Pipelining DSP48 output will improve performance

Jump to solution

Thanks.  

 

I just decided to use the IP Catalog and generate a DSP adder core instead of instantiating a primitive.  I'll see how that goes.  

 

 

View solution in original post

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