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emdoa
Newbie
Newbie
8,739 Views
Registered: ‎10-29-2014

Place:1115 - Unroutable Placement!

Hi,

I'm trying to Implement my design for Spartan-6 (xc6slx45--2fgg484). I'm using OpalKelly XEM6310 board.  I really don't know how i can resolve this issue.

 

I have problem with following part.

This board have LVDS 100MHz Clock connected to GCLK 28/29 ( AB11, Y11 - ug382).

an LVDS clock comes in on global clock pin pair and hits an IBUFGDS. The output of this buffer goes to a BUFIO2, whose DIVCLK output goes to a PLL's CLKIN. 

 

With this configuration i'm there is an error in the MAP process:

ERROR:Place:1115 - Unroutable Placement! A clock IOB / BUFIO clock component
   pair have been found that are not placed at a routable clock IOB / BUFIO site
   pair. The clock IOB component <sys_clkp> is placed at site <Y11>. The BUFIO
   component <ODDR_Test_Inst/BUFIO2_inst> is placed at site <BUFIO2_X0Y17>. Each
   BUFIO site has a select set of IOBs that can drive it. If these IOBs are not
   used, the connection is not routable You may want to analyze why this problem
   exists and correct it. This placement is UNROUTABLE in PAR and therefore,
   this error condition should be fixed in your design. You may use the
   CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
   WARNING in order to generate an NCD file. This NCD file can then be used in
   FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
_clkp" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN "ODDR_Test_Inst/BUFIO2_inst.I" CLOCK_DEDICATED_ROUTE = FALSE; >

 I read this thread < http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Insane-place-error-1115-in-S6/td-p/270200 > but I don't know if it's the right way.

When I add this path to ucf file, I can use FPGA Editor but Place&Route is still wrong.

Why ISE chose wrong BUFIO region for this GCLK pin and how i can change this? FPGA Editor is only possibility? I don't know this tools much and i need few tips how to start.

ISE 14.6

Thanks for any help

 

 

 

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3 Replies
vuppala
Xilinx Employee
Xilinx Employee
8,734 Views
Registered: ‎04-16-2012

Hello,

 

You can overcome this issue by placing the BUFIO2 in the correct site by using UCF constraint:

INST “instance_name” LOC=location;

i.e., INST "BUFIO2_inst" LOC=BUFIO2_X3Y7;

 

You can get the correct BUFIO2 location in UG382

 

Thanks,

Vinay

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user123random
Explorer
Explorer
201 Views
Registered: ‎05-02-2017

I faced almost similar error with xc6slx16-3ftg256

What is the correct site location for the following BUFIO2 for pin A10 ?

Note: I have read UG382 but I am not sure how to locate the correct locations.

 

 

ERROR:Place:1115 - Unroutable Placement! A clock IOB / BUFIO clock component
   pair have been found that are not placed at a routable clock IOB / BUFIO site
   pair. The clock IOB component <clk> is placed at site <A10>. The BUFIO
   component <SP6_BUFIO_INSERT_ML_BUFIO2_1> is placed at site <BUFIO2_X3Y0>.
   Each BUFIO site has a select set of IOBs that can drive it. If these IOBs are
   not used, the connection is not routable You may want to analyze why this
   problem exists and correct it. This placement is UNROUTABLE in PAR and
   therefore, this error condition should be fixed in your design. You may use
   the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message
   to a WARNING in order to generate an NCD file. This NCD file can then be used
   in FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
   < NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; >

ERROR:Place:1115 - Unroutable Placement! A clock IOB / BUFIO clock component
   pair have been found that are not placed at a routable clock IOB / BUFIO site
   pair. The clock IOB component <clk> is placed at site <A10>. The BUFIO
   component <SP6_BUFIO_INSERT_ML_BUFIO2_2> is placed at site <BUFIO2_X3Y10>.
   Each BUFIO site has a select set of IOBs that can drive it. If these IOBs are
   not used, the connection is not routable You may want to analyze why this
   problem exists and correct it. This placement is UNROUTABLE in PAR and
   therefore, this error condition should be fixed in your design. You may use
   the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message
   to a WARNING in order to generate an NCD file. This NCD file can then be used
   in FPGA Editor to debug the problem. A list of all the COMP.PINS used in this
   clock placement rule is listed below. These examples can be used directly in
   the .ucf file to demote this ERROR to a WARNING.
   < NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; >

 


 

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seamusbleu
Voyager
Voyager
165 Views
Registered: ‎08-12-2008

Isn't the information you need in Table 1-1 of UG382?

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