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Explorer
Explorer
14,071 Views
Registered: ‎06-19-2014

[Place 30-120] Sub-optimal placement for a BUFG-BUFG cascade pair.

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I am using Ac701 and  vivado 2014.2.

 

I have connection like

 

100 MHZ clock from MIG IP --> MMCM --> BUFG -- IDLEAYCTRL

 

While implementing design i get error

 

[Place 30-120] Sub-optimal placement for a BUFG-BUFG cascade pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets eth_200_clk/inst/eth_clk_200] >

    eth_200_clk/inst/clkout1_buf (BUFG.O) is provisionally placed by clockplacer on BUFGCTRL_X0Y15
     bufg_200_mhz (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
     trimode_eth_mac/example_clocks/bufg_clkin1 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y13

    The above error could possibly be related to other connected instances. Following is a list of
    all the related clock rules and their respective instances.

    Clock Rule: rule_mmcm_bufg
    Status: PASS
    Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
     eth_200_clk/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X0Y2
     eth_200_clk/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y12

    Clock Rule: rule_mmcm_bufg
    Status: PASS
    Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
     eth_200_clk/inst/mmcm_adv_inst (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X0Y2
     and eth_200_clk/inst/clkout1_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y15

 

 

My question is :

Why it tool is assigning BUFG instead of MMCM?

Untitled1.png
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Xilinx Employee
Xilinx Employee
22,704 Views
Registered: ‎09-20-2012

Hi,

 

Can you open synthesized design and run below command in TCL console?

 

show_objects -name find_1 [get_cells -hierarchical -filter { NAME =~  "*eth_200_clk/inst/clkout1_buf*" } ]

 

If this returns any cells, right click and select schematic. let me know if you see BUFG here.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
14,056 Views
Registered: ‎09-20-2012

Hi,

 

The error says that there are two cascaded BUFG instances in the design which are not placed in adjacent sites (in same half of the device).

 

I didnot get your query. Are you asking why is the tool inserting second BUFG on this path?

 

Why it tool is assigning BUFG instead of MMCM?

 

Thanks,

Deepika.

 

Thanks,
Deepika.
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Explorer
Explorer
14,050 Views
Registered: ‎06-19-2014

in the lines at end  eth_200_clk/inst/clkout1_buf (BUFG.O)  is detected as BUFG but it is MMCM (as shown in attached diagram).

 

This is my question that why tool has recognized MMCM as BUFG?

 

eth_200_clk/inst/clkout1_buf (BUFG.O) is provisionally placed by clockplacer on BUFGCTRL_X0Y15
bufg_200_mhz (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
trimode_eth_mac/example_clocks/bufg_clkin1 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y13

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Xilinx Employee
Xilinx Employee
22,705 Views
Registered: ‎09-20-2012

Hi,

 

Can you open synthesized design and run below command in TCL console?

 

show_objects -name find_1 [get_cells -hierarchical -filter { NAME =~  "*eth_200_clk/inst/clkout1_buf*" } ]

 

If this returns any cells, right click and select schematic. let me know if you see BUFG here.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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Explorer
Explorer
14,040 Views
Registered: ‎06-19-2014

here is the result.

Untitled2.png
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Xilinx Employee
Xilinx Employee
14,036 Views
Registered: ‎09-20-2012

Hi,

 

This confirms that the error is correct. eth_200_clk/inst/clkout1_buf is BUFG. This is not MMCM.

 

Check the connectivity of this BUFG (click on O and I pins) and attach another snapshot showing how many BUFG's are cascaded to this BUFG.

 

Thanks,

Deepika. 

Thanks,
Deepika.
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Explorer
Explorer
14,027 Views
Registered: ‎06-19-2014

Yes.. Now I see 2 BUFGs cascaded. Can i safely remove bufg_200_mhz and give output of MMCM to IDELAYCTRL?

Untitled2.png
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Xilinx Employee
Xilinx Employee
14,013 Views
Registered: ‎09-20-2012

Hi,

 

Yes, I think this BUFG can be removed as the driver is already another BUFG.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Explorer
Explorer
14,007 Views
Registered: ‎06-19-2014

thanks for helping me detect this hidden bufg :)

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Visitor
Visitor
13,686 Views
Registered: ‎07-22-2014

Hi,

 

I encountered a similar issue.

 

In my case however I can not remove the BUFGCE as it is needed to implement clockgating.

 

When I run an implementation with another version of this design (with exactly the same clockgating strategy) I do not see the issue.

 

What can I do?

 

[Place 30-120] Sub-optimal placement for a BUFG-BUFG cascade pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets VIVADO_WRAPPER/design_1_i/clk_wiz_0/U0/clk_out1] >

.....

 

Regards,

Jan

BufG.png
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Visitor
Visitor
6,945 Views
Registered: ‎12-10-2015

 

I came across the same problem that 'jangobin'.  Is there any solution instead of typing a CLOCK_DEDICATED_ROUTE FALSE  ¿?

 

Thanks!.

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Visitor
Visitor
1,910 Views
Registered: ‎04-06-2018

Hi,

 

I resolved this issue by having the outputs of the MMCM drive BUFH instead of BUFG (attached a snapshot). 

I tried the "No buffer " option also but, it would cause my MMCM lock to be low all the time - it would never get a lock signal.

 

--- Rajiv

mmcm_outputs_drive.jpg