[Place 30-140] Unroutable placement

[reshmaakhil]

Hi all, 

In my design I am using an optical interface and PCIe endpoint. I was able to test both individually and working fine. But when I tried to integrate both. It shows the following error. I didnt get a proper idea from the threads describing similar problems. So it would be great someone can suggest a way to solve this issue.  

I am using Kintex-7 FPGA(SOM-MIAMI-KINTEX7). And the pin mappings & .xci files are also attached. 

[Place 30-140] Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component pair is not placed in a routable site pair. The GTXE_COMMON component can use the dedicated path between the GTXE_COMMON and the GTXE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pcie/pcie_7x_0_support_i/pcie_7x_0_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/int_qplloutclk_out[0]] >

pcie/pcie_7x_0_support_i/pcie_7x_0_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gtx_common.gtxe2_common_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y1
pcie/pcie_7x_0_support_i/pcie_7x_0_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y2

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_gt_bufg
Status: PASS
Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
pcie/pcie_7x_0_support_i/pcie_7x_0_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i (GTXE2_CHANNEL.TXOUTCLK) is locked to GTXE2_CHANNEL_X0Y2
pcie/pcie_7x_0_support_i/pipe_clock_i/txoutclk_i.txoutclk_i (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y2

Clock Rule: rule_bufds_bufg
Status: PASS
Rule Description: A BUFDS driving a BUFG must be placed on the same half side (top/bottom) of the device
pcie/refclk_ibuf (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
pcie/pcie_7x_0_support_i/pcie_7x_0_i/U0/inst/gt_top_i/pipe_wrapper_i/cpllpd_refclk_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y1

Clock Rule: rule_bufds_gtxchannel_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTXChannel must both be placed in the same or adjacent clock region
(top/bottom)
pcie/refclk_ibuf (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
pcie/pcie_7x_0_support_i/pcie_7x_0_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y2

Clock Rule: rule_bufds_gtxcommon_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTXCommon must both be placed in the same or adjacent clock region
(top/bottom)
pcie/refclk_ibuf (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y0
and pcie/pcie_7x_0_support_i/pcie_7x_0_i/U0/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i/qpll_wrapper_i/gtx_common.gtxe2_common_i (GTXE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y1

Any help is appreciated.

Thanks & Regards,

Reshma 

[hongh]

Hi, @reshmaakhil ,

You need to check the LOC of your GT_COMMON and GT_CHANNEL.

The GT_COMMON is placed at "GTXE2_COMMON_X0Y1", and the compatible GT_CHANNEL shoud be "GTXE2_CHANNEL_X0Y4"~"GTXE2_CHANNEL_X0Y7". But the PCIe's GT_CHANNEL is placed at GTXE2_CHANNEL_X0Y2, which causes the issue.

You can try to move the GT_COMMON to GTXE2_COMMON_X0Y0.

[reshmaakhil]

Hi @hongh ,

Thanks a lot for your response.

But I am sorry to say that I dont know where I can do this correction. Is it in the .xdc  file?

The same is attached. 

Regards,

Reshma

[hongh]

Hi, @reshmaakhil ,

Please let me know your detailed device package and export your constraints after opening the synthesized design:

write_xdc XX.xdc

[reshmaakhil]

Hi,

The part number is XC7K325TFBG676.

And the xdc file generated is also attached.

Regards,

Reshma 

[marcb]

Hi @reshmaakhil 

Normally, I would suspect that the IO port driving the COMMON primitive in this case is in a separate clock region. However, I see that the Q0_CLK1_GTREFCLK_PAD_P_IN is in the same clock region as CHANNEL. Is Q0_CLK1_GTREFCLK_PAD_P_IN the port that drives the COMMON?

If so, another explaination is that another IP is using a COMMON block in the same clock region as the PCIe, so that the PCIe would need to use one from another clock region. If this does not explain the error, is a reproducible DCP available?

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