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Observer
Observer
258 Views
Registered: ‎07-02-2019

[Place 30-188] UnBuffered IOs

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Hi,

I met an error when doing implementation:

[Place 30-188] UnBuffered IOs: rst_i has following unbuffered loads :   DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_ENARDEN_cooolgate_en_gate_7(LUT3)   DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_ENBWREN_cooolgate_en_gate_9(LUT3)   DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_ENARDEN_cooolgate_en_gate_11(LUT3)   DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_ENBWREN_cooolgate_en_gate_13(LUT3)   DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_ENARDEN_cooolgate_en_gate_3(LUT3)   and DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_ENBWREN_cooolgate_en_gate_5(LUT3)

But according to https://www.xilinx.com/support/answers/62049.html, this issue is already solved in Vivado 2014.2. I am using Vivado 2019.1, Artix-7 FPGA.

Thanks for any comments.

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Highlighted
123 Views
Registered: ‎01-22-2015

Re: [Place 30-188] UnBuffered IOs

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@jiongsi 

I agree with hongh that you should further study the synthesis schematic for "rst_i".

However, I recognize those paths as being part of circuits added by Block-RAM (BRAM) power optimization.  -and, I've had problems with BRAM power optimization in the past.

You can try turning off BRAM power optimization as shown below.
NoBramPowerOpt.jpg

For more information on BRAM power optimization, see the following post.

https://forums.xilinx.com/t5/Implementation/No-valid-object-found-for-constraint-spec-command-copied/m-p/1104868#M28048

Mark

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Moderator
Moderator
169 Views
Registered: ‎11-04-2010

Re: [Place 30-188] UnBuffered IOs

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Hi, @jiongsi ,

What's schematic for the port "rst_i" and its loads?

Could you provide the opt.dcp for analysis?

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Re: [Place 30-188] UnBuffered IOs

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Hi @jiongsi ,

Also once check under sytnhesis setting whether the flatten_hierarchy option is set to None?

If yes then try to set it rebuilt and check whether it helps.

Thanks,

Raj

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Highlighted
124 Views
Registered: ‎01-22-2015

Re: [Place 30-188] UnBuffered IOs

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@jiongsi 

I agree with hongh that you should further study the synthesis schematic for "rst_i".

However, I recognize those paths as being part of circuits added by Block-RAM (BRAM) power optimization.  -and, I've had problems with BRAM power optimization in the past.

You can try turning off BRAM power optimization as shown below.
NoBramPowerOpt.jpg

For more information on BRAM power optimization, see the following post.

https://forums.xilinx.com/t5/Implementation/No-valid-object-found-for-constraint-spec-command-copied/m-p/1104868#M28048

Mark

View solution in original post

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Observer
Observer
103 Views
Registered: ‎07-02-2019

Re: [Place 30-188] UnBuffered IOs

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Thank you Mark, your solution works for me.

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