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n.russeil
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[Place 30-195] Unroutable Placement! A floating ILogic or OLogic component is not placed in a routable site pair....

Hi, 

I put in place two ISERDES for data and an concatenation of their .Q outputs to store them into one word. I use BUFIO, BUFR, IBUFGS to handle differential signals correctly. 

Now I want to use this word to transfer it into IP single port ram. But when I want to connect this word to my input port ram I have this implementation clock error about BUFR and iserdes output location :

 

[Place 30-195] Unroutable Placement! A floating ILogic or OLogic component is not placed in a routable site pair. The driver (BUFIO) and the floating load should be placed in the same clock region.
pack_Data_inst/bufferize_LVDS_inst1/bufio_inst (BUFIO.O) is locked to BUFIO_X0Y18
pack_Data_inst/bufferize_LVDS_inst1/pins[8].iserdes2_data_p (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X0Y242
pack_Data_inst/bufferize_LVDS_inst1/pins[8].iserdes2_data_n (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X0Y241
pack_Data_inst/bufferize_LVDS_inst1/pins[7].iserdes2_data_p (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X1Y244
pack_Data_inst/bufferize_LVDS_inst1/pins[7].iserdes2_data_n (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X1Y243
pack_Data_inst/bufferize_LVDS_inst1/pins[6].iserdes2_data_n (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X0Y244
pack_Data_inst/bufferize_LVDS_inst1/pins[5].iserdes2_data_n (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X0Y243
pack_Data_inst/bufferize_LVDS_inst1/pins[4].iserdes2_data_p (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X1Y246
pack_Data_inst/bufferize_LVDS_inst1/pins[4].iserdes2_data_n (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X1Y245
pack_Data_inst/bufferize_LVDS_inst1/pins[3].iserdes2_data_p (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X0Y246
pack_Data_inst/bufferize_LVDS_inst1/pins[3].iserdes2_data_n (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X0Y245
pack_Data_inst/bufferize_LVDS_inst1/pins[2].iserdes2_data_p (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X1Y248
pack_Data_inst/bufferize_LVDS_inst1/pins[2].iserdes2_data_n (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X1Y247
pack_Data_inst/bufferize_LVDS_inst1/pins[1].iserdes2_data_p (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X0Y248
pack_Data_inst/bufferize_LVDS_inst1/pins[1].iserdes2_data_n (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X0Y247
pack_Data_inst/bufferize_LVDS_inst1/pins[0].iserdes2_data_p (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X1Y249
pack_Data_inst/bufferize_LVDS_inst1/pins[0].iserdes2_data_n (ISERDESE2.CLK) is provisionally placed by clockplacer on ILOGIC_X0Y249

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_iotile_bufr
Status: PASS
Rule Description: An IO driving a BUFR must both be placed in the same clock region
pack_Data_inst/bufferize_LVDS_inst1/ibufds_clk_inst1 (IBUFDS.O) is locked to IOB_X0Y226
pack_Data_inst/bufferize_LVDS_inst1/clkout_buf_inst (BUFR.I) is provisionally placed by clockplacer on BUFR_X0Y19

Clock Rule: rule_bufh_bufr_ramb
Status: PASS
Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
than the capacity of the region
pack_Data_inst/bufferize_LVDS_inst1/clkout_buf_inst (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y19

Clock Rule: rule_bufio_bufr_clklds_floating
Status: FAIL
Rule Description: A BUFIO/BUFR driving any number of floating ILOGICs/OLOGICs/IDELAYs/ODELAYs (ones
without an associated IOB) must be placed within the same clock region
pack_Data_inst/bufferize_LVDS_inst1/clkout_buf_inst (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y19
pack_Data_inst/bufferize_LVDS_inst1/pins[8].iserdes2_data_p (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X0Y242
pack_Data_inst/bufferize_LVDS_inst1/pins[8].iserdes2_data_n (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X0Y241
pack_Data_inst/bufferize_LVDS_inst1/pins[7].iserdes2_data_p (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X1Y244
pack_Data_inst/bufferize_LVDS_inst1/pins[7].iserdes2_data_n (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X1Y243
pack_Data_inst/bufferize_LVDS_inst1/pins[6].iserdes2_data_n (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X0Y244
pack_Data_inst/bufferize_LVDS_inst1/pins[5].iserdes2_data_n (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X0Y243
pack_Data_inst/bufferize_LVDS_inst1/pins[4].iserdes2_data_p (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X1Y246
pack_Data_inst/bufferize_LVDS_inst1/pins[4].iserdes2_data_n (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X1Y245
pack_Data_inst/bufferize_LVDS_inst1/pins[3].iserdes2_data_p (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X0Y246
pack_Data_inst/bufferize_LVDS_inst1/pins[3].iserdes2_data_n (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X0Y245
pack_Data_inst/bufferize_LVDS_inst1/pins[2].iserdes2_data_p (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X1Y248
pack_Data_inst/bufferize_LVDS_inst1/pins[2].iserdes2_data_n (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X1Y247
pack_Data_inst/bufferize_LVDS_inst1/pins[1].iserdes2_data_p (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X0Y248
pack_Data_inst/bufferize_LVDS_inst1/pins[1].iserdes2_data_n (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X0Y247
pack_Data_inst/bufferize_LVDS_inst1/pins[0].iserdes2_data_p (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X1Y249
and pack_Data_inst/bufferize_LVDS_inst1/pins[0].iserdes2_data_n (ISERDESE2.CLKDIV) is provisionally placed by clockplacer on ILOGIC_X0Y249
ERROR: The above is also an illegal clock rule
Workaround: < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets pack_Data_inst/bufferize_LVDS_inst1/CLK_DIV] >

 

 

So, I don't understand in my .xdc file how to solve this problem, how to choose the good clock region to implement all these signals ? 

Thanks

Nathan

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n.russeil
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Registered: ‎09-21-2018

Nobody to help me ?

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syedz
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@n.russeil 

 

I believe this is a 7 series device. If yes, you are violating the rule where BUFIO loads should all be placed in a single clock region. Check table 1-1 in the below 7 series clocking resource user guide:

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf#page=24  

image.png

Also, check this similar forums thread: https://forums.xilinx.com/t5/Other-FPGA-Architecture/Place-design-error-30-195/td-p/679117 

 

--Syed

 

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n.russeil
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Hi @syedz, thanks for your reply

 

I understand that I violated BUFIO rule. So, to resolve this in my constraint .xdc file I put BUFIO and all the ILOGIC and OLOGIC within the same clock region thanks to "set_property LOC" command. However, the problem persists...

 

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syedz
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@n.russeil 

 

Can you share the post opt dcp file after you have applied the LOC constraint? Use this AR to debug the issue: https://www.xilinx.com/support/answers/67203.html  

 

--Syed

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n.russeil
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Attached, find my opt dcp file with LOC constraints applied

 

Note that I work with Artix7.

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syedz
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@n.russeil 

 

Can you please recheck the dcp which you shared, I am unable to reproduce the  same error. The commands used are:
open_checkpoint ./numerisation_data_debug_opt.dcp
opt_design
place_design

ERROR: [Place 30-806] Clock placer fails to converge to a solution. Please try to LOC the following instances, which may allow clock placer to converge and find a legal solution:
Driver inst: pack_Data_inst/bufferize_LVDS_inst1/bufio_inst
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[7].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[8].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[8].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[7].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[0].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[0].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[1].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[1].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[2].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[2].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[3].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[3].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[4].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[4].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[5].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[6].iserdes2_data_n

Driver inst: pack_Data_inst/bufferize_LVDS_inst1/clkout_buf_inst
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[7].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[8].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[8].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[7].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[0].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[0].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[1].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[1].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[2].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[2].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[3].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[3].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[4].iserdes2_data_p
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[4].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[5].iserdes2_data_n
Load inst: pack_Data_inst/bufferize_LVDS_inst1/pins[6].iserdes2_data_n

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n.russeil
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Tell me if this file it's ok. Note that I'm working under Vivado 2014.4

 

 

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n.russeil
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Is it ok @syedz ?

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syedz
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@n.russeil 

 

I was able to reproduce the error in 2014.4, I still see the violation where loads of BUFR is spread across multiple clock region but it can only drive loads in single clock region:

image.png

 

image.png

 

I used place_ports command to get the above schematic with locations: https://www.xilinx.com/support/answers/67203.html  

 

--Syed

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n.russeil
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@syedz 

Yes, like you, in my side  I'm seeing the same multiple clock region use of BUFR.

However, something is strange. In .xdc file I put LOC constraint to place all these signals into same clock region but it doesn't seem to be considered when executing place_ports command..

Constraints used : 

set_property LOC ILOGIC_X0Y225 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[0].iserdese2_data_p}]
set_property LOC ILOGIC_X0Y226 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[0].iserdese2_data_n}]
set_property LOC ILOGIC_X0Y227 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[1].iserdese2_data_p}]
set_property LOC ILOGIC_X0Y228 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[1].iserdese2_data_n}]
set_property LOC ILOGIC_X0Y229 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[2].iserdese2_data_p}]
set_property LOC ILOGIC_X0Y230 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[2].iserdese2_data_n}]
set_property LOC ILOGIC_X0Y231 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[3].iserdese2_data_p}]
set_property LOC ILOGIC_X0Y232 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[3].iserdese2_data_n}]
set_property LOC ILOGIC_X0Y233 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[4].iserdese2_data_p}]
set_property LOC ILOGIC_X0Y234 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[4].iserdese2_data_n}]
set_property LOC ILOGIC_X0Y235 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[5].iserdese2_data_p}]
set_property LOC ILOGIC_X0Y236 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[5].iserdese2_data_n}]
set_property LOC ILOGIC_X0Y237 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[6].iserdese2_data_p}]
set_property LOC ILOGIC_X0Y238 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[6].iserdese2_data_n}]
set_property LOC ILOGIC_X0Y239 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[7].iserdese2_data_p}]
set_property LOC ILOGIC_X0Y240 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[7].iserdese2_data_n}]
set_property LOC ILOGIC_X0Y241 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[8].iserdese2_data_p}]
set_property LOC ILOGIC_X0Y242 [get_cells {pack_Data_inst/bufferize_LVDS_inst1/pins[8].iserdese2_data_n}]

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Registered: ‎01-22-2015

@n.russeil  

You said that errors started after you added IP single port ram (BRAM) to the design. Although errors point to other components, maybe you need LOC constraints on the BRAM to place it in the clocking region of the BUFR.

Cheers, Mark

n.russeil
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markg@prosensing.com @syedz 

I tried your suggestion, I put all RAM port into the same BUFR clocking region thanks to LOC constraints but I doesn't worked... 

One more time I think my LOC constraint were not considered...

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@n.russeil 

One more time I think my LOC constraint were not considered...
Ok.  You are using an old (v2014.4) version of Vivado.  So, maybe LOC was not working so well back then.

Try the other clocking architecture for ISERDES suggested on page 153 of UG471.  That is, use an MMCM and BUFGs to drive the clock inputs of ISERDES.  With the BUFG, there will be no clocking region restrictions and you will not need to use LOC constraints.  

 

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n.russeil
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markg@prosensing.com 

Good point, Maybe v2014.4 vivado version is too old...I will install the last one to try ! 

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