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Scholar muravin
Scholar
497 Views
Registered: ‎11-21-2013

[Place 30-365] The following macros could not be placed - weird problem

Hello,

We are trying to fit our design into the XCZU3 FPGA. Pre-synthesis resource usage is:

- 69k/70.4k LUTs

- 47k/141k FFs

- 197/216 BRAMs

- 221/320 DSPs

So, none off the above exceeds 100%. My issue is that in the following error, the DSP utilizatrion shows up as 491. We have no problem fitting the same design into the XCZU6/9 and the design still uses 221 DSP blocks after place/route for the XCZU6/9. Synthesis settings for max dsp blocks set to 0. What is the meaning of this error then? How do one get to 491 DSP blocks?

Thank you

Vlad

[Place 30-365] The following macros could not be placed:
system_i/inst_tcon/inst/inst_memory_interface/inst_tcon_bram_if/inst_DP_RAM_64x32_Sequence_Addr/infer_bram.speed.inst_tdpbram/mem_reg_bram_0 (RAMB36E2)
system_i/inst_tcon/inst/inst_memory_interface/inst_tcon_bram_if/INST_1024_DEEP_BRAM.inst_DP_RAM_1024x32_Segment_State/infer_bram.speed.inst_tdpbram/mem_reg_bram_0 (RAMB36E2)
system_i/inst_tcon/inst/inst_memory_interface/inst_tcon_bram_if/INST_1024_DEEP_BRAM.inst_DP_RAM_1024x32_Segment_Timestamp/infer_bram.speed.inst_tdpbram/mem_reg_bram_0 (RAMB36E2)
and system_i/inst_tcon/inst/inst_memory_interface/inst_tcon_bram_if/inst_DP_RAM_64x32_Sequence_Repeats/infer_bram.speed.inst_tdpbram/mem_reg_bram_0 (RAMB36E2)
The total BRAM utilization is 91.2, the total DSP utilization is 491.1 and the total URAM utilization is 0
A possible reason is high utilization of BRAMs, DSPs, URAMs, or RPMs. Please check user constraints to make sure design is not over-utilized in the constraint areas (if any) keeping in mind some macros require a number of consecutively available sites

 

Vladislav Muravin
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9 Replies
Moderator
Moderator
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Registered: ‎01-16-2013

Re: [Place 30-365] The following macros could not be placed - weird problem

@muravin

 

Does the design contain IP which are run in OOC mode? The post synth utilization will not report the utilization with IP in OOC mode as these are considered as black box in synthesis run. Try opening the synthesized design and run :

1. opt_design 

2. report_utilization

We are checking the utilization before running place_design.

 

--Syed

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Scholar muravin
Scholar
460 Views
Registered: ‎11-21-2013

Re: [Place 30-365] The following macros could not be placed - weird problem

Hi @syedz,

Thank you for the prompt response.

Yes, the design has the OOC synthesis for all of our IPs. BTW, this is VIVADO 2017.4, Linux x64.

I have done what you had suggested, and the report_utilization after the opt_design shows 221 DSP blocks as expected, see below. 

Vlad

report_utilization
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Tue Nov 27 10:04:59 2018
| Host : fpgadev.ignis.ca running 64-bit Red Hat Enterprise Linux Server release 6.4 (Santiago)
| Command : report_utilization
| Design : system_wrapper
| Device : xczu3egsfvc784-1
| Design State : Synthesized
--------------------------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists

1. CLB Logic
------------

+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| CLB LUTs* | 67872 | 0 | 70560 | 96.19 |
| LUT as Logic | 57604 | 0 | 70560 | 81.64 |
| LUT as Memory | 10268 | 0 | 28800 | 35.65 |
| LUT as Distributed RAM | 7446 | 0 | | |
| LUT as Shift Register | 2822 | 0 | | |
| CLB Registers | 45562 | 0 | 141120 | 32.29 |
| Register as Flip Flop | 45556 | 0 | 141120 | 32.28 |
| Register as Latch | 6 | 0 | 141120 | <0.01 |
| CARRY8 | 1303 | 0 | 8820 | 14.77 |
| F7 Muxes | 1229 | 0 | 35280 | 3.48 |
| F8 Muxes | 201 | 0 | 17640 | 1.14 |
| F9 Muxes | 0 | 0 | 8820 | 0.00 |
+----------------------------+-------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 356 | Yes | - | Set |
| 3348 | Yes | - | Reset |
| 546 | Yes | Set | - |
| 41312 | Yes | Reset | - |
+-------+--------------+-------------+--------------+


2. BLOCKRAM
-----------

+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 197 | 0 | 216 | 91.20 |
| RAMB36/FIFO* | 164 | 0 | 216 | 75.93 |
| FIFO36E2 only | 103 | | | |
| RAMB36E2 only | 61 | | | |
| RAMB18 | 66 | 0 | 432 | 15.28 |
| FIFO18E2 only | 56 | | | |
| RAMB18E2 only | 10 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2


3. ARITHMETIC
-------------

+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 221 | 0 | 360 | 61.39 |
| DSP48E2 only | 221 | | | |
+----------------+------+-------+-----------+-------+


4. I/O
------

+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| Bonded IOB | 151 | 0 | 252 | 59.92 |
+------------+------+-------+-----------+-------+


5. CLOCK
--------

+----------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------+------+-------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 10 | 0 | 196 | 5.10 |
| BUFGCE | 8 | 0 | 88 | 9.09 |
| BUFGCE_DIV | 0 | 0 | 12 | 0.00 |
| BUFG_PS | 2 | 0 | 72 | 2.78 |
| BUFGCTRL* | 0 | 0 | 24 | 0.00 |
| PLL | 0 | 0 | 6 | 0.00 |
| MMCM | 2 | 0 | 3 | 66.67 |
+----------------------+------+-------+-----------+-------+
* Note: Each used BUFGCTRL counts as two global buffer resources. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.


6. ADVANCED
-----------

+-----------+------+-------+-----------+--------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+--------+
| PS8 | 1 | 0 | 1 | 100.00 |
| SYSMONE4 | 0 | 0 | 1 | 0.00 |
+-----------+------+-------+-----------+--------+


7. CONFIGURATION
----------------

+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 1 | 0 | 4 | 25.00 |
| DNA_PORTE2 | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 1 | 0.00 |
| ICAPE3 | 0 | 0 | 2 | 0.00 |
| MASTER_JTAG | 0 | 0 | 1 | 0.00 |
| STARTUPE3 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+


8. Primitives
-------------

+------------+-------+---------------------+
| Ref Name | Used | Functional Category |
+------------+-------+---------------------+
| FDRE | 41312 | Register |
| LUT6 | 28293 | CLB |
| LUT5 | 12901 | CLB |
| LUT4 | 9475 | CLB |
| LUT3 | 6568 | CLB |
| LUT2 | 6422 | CLB |
| RAMD32 | 4982 | CLB |
| FDCE | 3342 | Register |
| RAMS32 | 2844 | CLB |
| SRL16E | 2604 | CLB |
| CARRY8 | 1303 | CLB |
| MUXF7 | 1229 | CLB |
| LUT1 | 999 | CLB |
| FDSE | 546 | Register |
| FDPE | 356 | Register |
| RAMS64E | 320 | CLB |
| SRLC32E | 276 | CLB |
| DSP48E2 | 221 | Arithmetic |
| MUXF8 | 201 | CLB |
| OBUF | 124 | I/O |
| FIFO36E2 | 103 | Block Ram |
| RAMB36E2 | 61 | Block Ram |
| FIFO18E2 | 56 | Block Ram |
| RAMD64E | 52 | CLB |
| OSERDESE3 | 18 | I/O |
| INV | 18 | CLB |
| IBUFCTRL | 18 | Others |
| RAMB18E2 | 10 | Block Ram |
| ISERDESE3 | 9 | I/O |
| INBUF | 9 | I/O |
| DIFFINBUF | 9 | I/O |
| IDELAYE3 | 8 | I/O |
| BUFGCE | 8 | Clock |
| SRLC16E | 6 | CLB |
| LDCE | 6 | Register |
| MMCME4_ADV | 2 | Clock |
| BUFG_PS | 2 | Clock |
| PS8 | 1 | Advanced |
| IDELAYCTRL | 1 | I/O |
| BSCANE2 | 1 | Configuration |
+------------+-------+---------------------+


9. Black Boxes
--------------

+----------+------+
| Ref Name | Used |
+----------+------+


10. Instantiated Netlists
-------------------------

+-----------------------------------+------+
| Ref Name | Used |
+-----------------------------------+------+
| system_zynq_ultra_ps_e_0_0 | 1 |
| system_xlconstant_1b1_0 | 1 |
| system_xlconcat_tbus_clk_0 | 1 |
| system_xlconcat_tbus3_0 | 1 |
| system_xlconcat_tbus2_0 | 1 |
| system_xlconcat_tbus1_0 | 1 |
| system_xlconcat_tbus0_0 | 1 |
| system_xbar_1 | 1 |
| system_xbar_0 | 1 |
| system_tier2_xbar_2_0 | 1 |
| system_tier2_xbar_1_0 | 1 |
| system_tier2_xbar_0_0 | 1 |
| system_proc_sys_reset_hdmi_0 | 1 |
| system_proc_sys_reset_dsp_0 | 1 |
| system_proc_sys_reset_100mhz_0 | 1 |
| system_inst_udp_ip_0 | 1 |
| system_inst_testpad_mux_0 | 1 |
| system_inst_testbus_mux_0 | 1 |
| system_inst_tcon_0 | 1 |
| system_inst_sys_reset_serdes_0 | 1 |
| system_inst_pnldrv_0 | 1 |
| system_inst_pnlccb_0 | 1 |
| system_inst_meas_gen_0 | 1 |
| system_inst_meas_ctrl_0 | 1 |
| system_inst_lvds_receiver_0 | 1 |
| system_inst_interp_filter_0 | 1 |
| system_inst_ignis_zynq_udp_intf_0 | 1 |
| system_inst_ignis_vidsrc_0 | 1 |
| system_inst_ignis_vdma_vidsink_0 | 1 |
| system_inst_ignis_vdma_auxsink_0 | 1 |
| system_inst_ignis_dma_0 | 1 |
| system_inst_huffman_decoder_0 | 1 |
| system_inst_gokutcon_mapper_0 | 1 |
| system_inst_cmpipe_0 | 1 |
| system_inst_clkgen_serdes_0 | 1 |
| system_axi_fifo_mm_s_1_0 | 1 |
| system_auto_us_1 | 1 |
| system_auto_us_0 | 1 |
| system_auto_pc_3 | 1 |
| system_auto_pc_2 | 1 |
| system_auto_pc_1 | 1 |
| system_auto_pc_0 | 1 |
+-----------------------------------+------+


report_utilization: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 10866.637 ; gain = 0.000 ; free physical = 26929 ; free virtual = 32795

Vladislav Muravin
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Scholar muravin
Scholar
443 Views
Registered: ‎11-21-2013

Re: [Place 30-365] The following macros could not be placed - weird problem

Hi @syedz

If this would help, I can share the design checkpoint via an EZMove link, so that Xilinx can reproduce this.

BR

Vlad

Vladislav Muravin
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Registered: ‎01-16-2013

Re: [Place 30-365] The following macros could not be placed - weird problem

@muravin

 

I have sent you email from ezmove. Please upload the post opt dcp file and send it back to us for debugging.

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

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---------------------------------------------------------------------------------------------
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Scholar muravin
Scholar
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Registered: ‎11-21-2013

Re: [Place 30-365] The following macros could not be placed - weird problem

Hy @syedz

I have figured (or guessed) out the issue.

Basically, it is the allocation of the BRAM into cascaded macros that is likely failing. So the total BRAM usage is less than 100% but the macros cannot be placed.

That being said, there is still a bug in the reporting of this problem, i.e. the VIVADO says that it is the DSP block usage that is 471%. So I will upload the DCP at the provided link.

Thank you very much

Vlad

Vladislav Muravin
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Registered: ‎01-16-2013

Re: [Place 30-365] The following macros could not be placed - weird problem

@muravin

 

Can you check in latest released vivado 2018.3?

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Scholar muravin
Scholar
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Registered: ‎11-21-2013

Re: [Place 30-365] The following macros could not be placed - weird problem

@syedz

No I did not, but we will be installing it and trying right after the holidays. I will let you know how it goes.

Merry Christmas and Happy New Year

Vlad

Vladislav Muravin
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Registered: ‎01-16-2013

Re: [Place 30-365] The following macros could not be placed - weird problem

@muravin

 

Can you update back on this open thread?

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Scholar muravin
Scholar
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Registered: ‎11-21-2013

Re: [Place 30-365] The following macros could not be placed - weird problem

Hi @syedz

The issue still exists with the latest VIVADO, but I believe that the issue is caused by specific BRAM macro concatenation, which cannot be placed, even if the total BRAM usage is less than 100%.

We did find a solution by reorganizing the BRAMs.

Cheers

Vlad

Vladislav Muravin
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