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Visitor kirito0816
Visitor
388 Views
Registered: ‎11-26-2018

[Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed. (with NO RLDRAM3 IN DESIGN)

Hello,

I meet this problem recently in Vivado 2016.4:

[Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed.

Number of LUTRAMs: 5299
Number of LUTRAM capable slices required is 1552 out of 73980 in the device (utilization 2.09786%)

Even though there is a sufficient number of LUTRAM capable slices in the device, the packing algorithm was not able to find a solution. Please analyze your design to determine if the number of LUTRAMs can be reduced.

As a result, 1 LUTRAMs failed to place.
Names of these LUTRAMs:
u_ila_0/inst/ila_core_inst/shifted_data_in_reg[7][656]_srl8 type SRL16E

The mentioned LUTRAMs are constrained as below: (listing maximum of 20 LUTRAMs per constraint)
An interal area constraint:
u_ila_0/inst/ila_core_inst/shifted_data_in_reg[7][656]_srl8

Number of LUTRAM capable slices required* by this constraint: 164
Number of LUTRAM capable slices available in this constraint region: 24660
Utilization = 0%

* - The number of LUTRAM capable slices required is computed under assumption that the LUTRAMs can be perfectly packed in the constrained region. Also, each LUTRAM may be a macro containing multiple LUTRAM instances.


Resolution: Please analyze your design to determine if the number of lutrams can be reduced by combining multiple lutrams into Block RAMs for example.

Then I find the solution of this site: "https://www.xilinx.com/support/answers/66589.html". I did not use any RLDRAM3 but I tried it anyway. The only MIG module in my design is DDR4. So I follow the solution and draw a pblock on DDR4. There is still an error.

I have 1 PCIE core, 1 axi_clock_converter, 1 DDR4 and 1 FIFO using BRAM in my design. When I add a debug core, there comes out this problem. I don't know how can I find the related information about the LUTRAM fail to be placed: "u_ila_0/inst/ila_core_inst/shifted_data_in_reg[7][656]_srl8 type SRL16E". Thank you.

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5 Replies
Moderator
Moderator
385 Views
Registered: ‎01-16-2013

Re: [Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed. (with NO RLDRAM3 IN DESIGN)

@kirito0816

 

Is it possible for you to try in the latest 2018.2 with different implementation strategies? Can you share the post opt dcp file located at <project>/<project>.runs/impl_1/***_opt.dcp?

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Visitor kirito0816
Visitor
367 Views
Registered: ‎11-26-2018

Re: [Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed. (with NO RLDRAM3 IN DESIGN)

Thank you for your response. I did not try it in 2018.2. But I find a result that once I use the mark debug to add the "inout" type signal in VHDL, I will get this problem. And It shows that the file is too big to be uploaded.

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Visitor sacatak
Visitor
204 Views
Registered: ‎10-27-2016

Re: [Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed. (with NO RLDRAM3 IN DESIGN)

Dear kirto0816,

I've exactly the same problem ( I use Vivado 2017.4) and I don't really understand the message seen that the design is very small.

Do you have fund a fix for that?

 

The error message that I have is:

ERROR: [Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed.

Number of LUTRAMs: 30196
Number of LUTRAM capable slices required is 7943 out of 43550 in the device (utilization 18.2388%)

Even though there is a sufficient number of LUTRAM capable slices in the device, the packing algorithm was not able to find a solution. Please analyze your design to determine if the number of LUTRAMs can be reduced.

As a result, 20 or more LUTRAMs failed to place.
Names of the first 20 LUTRAMs:
C_TOP_TIGER_FPGA/C_DAQ_VIRTUAL_FIFO/C_AXIS_PDW_CLOCK_CONVERTER_16B/inst/gen_fifo_gen_ck_conv.axis_data_fifo_0/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_5 type RAM32M16
C_TOP_TIGER_FPGA/C_DAQ_VIRTUAL_FIFO/C_AXIS_PDW_CLOCK_CONVERTER_16B/inst/gen_fifo_gen_ck_conv.axis_data_fifo_0/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_5 type RAM32M16
--
C_TOP_TIGER_FPGA/C_DAQ_VIRTUAL_FIFO/C_AXIS_PDW_CLOCK_CONVERTER_16B/inst/gen_fifo_gen_ck_conv.axis_data_fifo_0/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_5 type RAM32M16
C_TOP_TIGER_FPGA/C_DAQ_VIRTUAL_FIFO/C_AXIS_PDW_CLOCK_CONVERTER_16B/inst/gen_fifo_gen_ck_conv.axis_data_fifo_0/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_5 type RAM32M16
C_TOP_TIGER_FPGA/C_DAQ_VIRTUAL_FIFO/C_AXIS_PDW_CLOCK_CONVERTER_16B/inst/gen_fifo_gen_ck_conv.axis_data_fifo_0/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_6_11 type RAM32M16
C_TOP_TIGER_FPGA/C_DAQ_VIRTUAL_FIFO/C_AXIS_PDW_CLOCK_CONVERTER_16B/inst/gen_fifo_gen_ck_conv.axis_data_fifo_0/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_6_11 type RAM32M16
C_TOP_TIGER_FPGA/C_DAQ_VIRTUAL_FIFO/C_AXIS_PDW_CLOCK_CONVERTER_16B/inst/gen_fifo_gen_ck_conv.axis_data_fifo_0/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_6_11 type RAM32M16
C_TOP_TIGER_FPGA/C_DAQ_VIRTUAL_FIFO/C_AXIS_PDW_CLOCK_CONVERTER_16B/inst/gen_fifo_gen_ck_conv.axis_data_fifo_0/gen_fifo_generator.fifo_generator_inst/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_6_11 type RAM32M16

None of mentioned LUTRAMs is from any Pblock.

Resolution: Please analyze your design to determine if the number of lutrams can be reduced by combining multiple lutrams into Block RAMs for example.
ERROR: [Place 30-99] Placer failed with error: 'Could not place all lutrams'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 1ee33ee8

 

 

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Visitor sacatak
Visitor
183 Views
Registered: ‎10-27-2016

Re: [Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed. (with NO RLDRAM3 IN DESIGN)

I answer to myself.

I fix the problem by driving an unusued internal inout signal by 'Z' instead of '0'.

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Xilinx Employee
Xilinx Employee
132 Views
Registered: ‎05-08-2012

Re: [Place 30-484] The packing of lutram instances into lutram capable slices could not be obeyed. (with NO RLDRAM3 IN DESIGN)

Hi @kirito0816.

If you follow the D pin of the SRL in the error, does this net have more than one driver? If yes, this would be causing the failure. What is happening is that the MARK_DBUG property prevents optmization. When hierarchies connected to the ILA contain INOUT ports, the hierarchy port is counted as a driver, even though it is not a leaf cell. Removing the multiple drivers will remove the placement error.


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