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Adventurer
Adventurer
385 Views
Registered: ‎12-26-2016

Place 30-504 Error

Hi there,

I have the following error during implementation on Vivado 2018.2:

[Place 30-504] Global clock placer failed to legalize CLOCKREGION_X1Y0 for clock loads of type DSP48E1. This region contains 40 available DSP48E1 sites, however there are 54 such loads in the region and clock legalizer could not move enough loads out of the region to legalize it. The following clock nets have loads of type DSP48E1 in this region:
Clock net: myDesign_i/processing_system7_0/inst/FCLK_CLK0
Driver: myDesign_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG
Number of DSP48E1 loads: 36
If the clock net(s) are regional, try using global clock buffers to drive the loads so they are not restricted to specific clock regions and have more freedom to move.

However, the design is not completely full; after opening synthesized design and running report_utilization I got:

1. Slice Logic
--------------

+----------------------------+-------+-------+-----------+-------+
|          Site Type         |  Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs*                | 18368 |     0 |     53200 | 34.53 |
|   LUT as Logic             | 14426 |     0 |     53200 | 27.12 |
|   LUT as Memory            |  3942 |     0 |     17400 | 22.66 |
|     LUT as Distributed RAM |   722 |     0 |           |       |
|     LUT as Shift Register  |  3220 |     0 |           |       |
| Slice Registers            | 36208 |     0 |    106400 | 34.03 |
|   Register as Flip Flop    | 36208 |     0 |    106400 | 34.03 |
|   Register as Latch        |     0 |     0 |    106400 |  0.00 |
| F7 Muxes                   |   239 |     0 |     26600 |  0.90 |
| F8 Muxes                   |     0 |     0 |     13300 |  0.00 |
+----------------------------+-------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0     |            _ |           - |            - |
| 0     |            _ |           - |          Set |
| 0     |            _ |           - |        Reset |
| 0     |            _ |         Set |            - |
| 0     |            _ |       Reset |            - |
| 0     |          Yes |           - |            - |
| 12    |          Yes |           - |          Set |
| 23    |          Yes |           - |        Reset |
| 996   |          Yes |         Set |            - |
| 35177 |          Yes |       Reset |            - |
+-------+--------------+-------------+--------------+


2. Memory
---------

+-------------------+------+-------+-----------+-------+
|     Site Type     | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile    |  110 |     0 |       140 | 78.57 |
|   RAMB36/FIFO*    |   18 |     0 |       140 | 12.86 |
|     RAMB36E1 only |   18 |       |           |       |
|   RAMB18          |  184 |     0 |       280 | 65.71 |
|     RAMB18E1 only |  184 |       |           |       |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1


3. DSP
------

+----------------+------+-------+-----------+-------+
|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs           |  174 |     0 |       220 | 79.09 |
|   DSP48E1 only |  174 |       |           |       |
+----------------+------+-------+-----------+-------+


4. IO and GT Specific
---------------------

+-----------------------------+------+-------+-----------+--------+
|          Site Type          | Used | Fixed | Available |  Util% |
+-----------------------------+------+-------+-----------+--------+
| Bonded IOB                  |   91 |    91 |       125 |  72.80 |
|   IOB Master Pads           |   45 |       |           |        |
|   IOB Slave Pads            |   44 |       |           |        |
| Bonded IPADs                |    0 |     0 |         2 |   0.00 |
| Bonded IOPADs               |  130 |   130 |       130 | 100.00 |
| PHY_CONTROL                 |    0 |     0 |         4 |   0.00 |
| PHASER_REF                  |    0 |     0 |         4 |   0.00 |
| OUT_FIFO                    |    0 |     0 |        16 |   0.00 |
| IN_FIFO                     |    0 |     0 |        16 |   0.00 |
| IDELAYCTRL                  |    0 |     0 |         4 |   0.00 |
| IBUFDS                      |    0 |     0 |       121 |   0.00 |
| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        16 |   0.00 |
| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        16 |   0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       200 |   0.00 |
| ILOGIC                      |    0 |     0 |       125 |   0.00 |
| OLOGIC                      |   20 |    13 |       125 |  16.00 |
|   OUTFF_ODDR_Register       |    4 |     4 |           |        |
|   OSERDES                   |   16 |     9 |           |        |
|   ODDR                      |    1 |       |           |        |
+-----------------------------+------+-------+-----------+--------+


5. Clocking
-----------

+------------+------+-------+-----------+-------+
|  Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL   |   15 |     0 |        32 | 46.88 |
| BUFIO      |    0 |     0 |        16 |  0.00 |
| MMCME2_ADV |    1 |     0 |         4 | 25.00 |
| PLLE2_ADV  |    2 |     0 |         4 | 50.00 |
| BUFMRCE    |    0 |     0 |         8 |  0.00 |
| BUFHCE     |    0 |     0 |        72 |  0.00 |
| BUFR       |    0 |     0 |        16 |  0.00 |
+------------+------+-------+-----------+-------+


6. Specific Feature
-------------------

+-------------+------+-------+-----------+-------+
|  Site Type  | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2     |    0 |     0 |         4 |  0.00 |
| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
| DNA_PORT    |    0 |     0 |         1 |  0.00 |
| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
| ICAPE2      |    0 |     0 |         2 |  0.00 |
| STARTUPE2   |    0 |     0 |         1 |  0.00 |
| XADC        |    0 |     0 |         1 |  0.00 |
+-------------+------+-------+-----------+-------+


7. Primitives
-------------

+------------+-------+----------------------+
|  Ref Name  |  Used |  Functional Category |
+------------+-------+----------------------+
| FDRE       | 35177 |         Flop & Latch |
| LUT3       |  5682 |                  LUT |
| LUT6       |  3586 |                  LUT |
| SRL16E     |  3110 |   Distributed Memory |
| LUT5       |  2683 |                  LUT |
| LUT4       |  2336 |                  LUT |
| LUT2       |  2141 |                  LUT |
| LUT1       |  1535 |                  LUT |
| FDSE       |   996 |         Flop & Latch |
| RAMD32     |   938 |   Distributed Memory |
| RAMS32     |   312 |   Distributed Memory |
| CARRY4     |   312 |           CarryLogic |
| MUXF7      |   239 |                MuxFx |
| RAMB18E1   |   184 |         Block Memory |
| DSP48E1    |   174 |     Block Arithmetic |
| BIBUF      |   130 |                   IO |
| SRLC32E    |   110 |   Distributed Memory |
| RAMD64E    |    96 |   Distributed Memory |
| OBUF       |    53 |                   IO |
| IBUF       |    38 |                   IO |
| FDCE       |    23 |         Flop & Latch |
| RAMB36E1   |    18 |         Block Memory |
| OSERDESE2  |    16 |                   IO |
| BUFG       |    15 |                Clock |
| FDPE       |    12 |         Flop & Latch |
| ODDR       |     5 |                   IO |
| PLLE2_ADV  |     2 |                Clock |
| PS7        |     1 | Specialized Resource |
| MMCME2_ADV |     1 |                Clock |
+------------+-------+----------------------+

Resetting output products didn't help.

Does anyone has an idea where the error could be?

Cheers
Thomas

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4 Replies
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Xilinx Employee
Xilinx Employee
345 Views
Registered: ‎05-08-2012

Re: Place 30-504 Error

Hi @tmaintz 

The message is indicating that the placer could not move the loads to make the successfull placement. Are there any constraints (pblock, LOC, or other) that would affect the placement?

The issue might be that the clock partitioner has not allocated enough clock regions. Can you post the output files from the below command?

report_clock_utilization -file clk_util.rpt -write_xdc clk_util_floorplan.xdc
---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
Highlighted
Adventurer
Adventurer
297 Views
Registered: ‎12-26-2016

Re: Place 30-504 Error

Hi @marcb 

I have attached the files you asked for. Do you need any additional information?

Cheers
Thomas

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Xilinx Employee
Xilinx Employee
265 Views
Registered: ‎05-08-2012

Re: Place 30-504 Error

Hi @tmaintz 

Could you actually run place_ports before the suggested command? The placer error looks to have removed the progress, so using place_ports instead of place_design should save the IO & Clock placement portion of placement. The XDC output from the report_clock_utilization should contain pblocks related to each clock. We want to see how many CLOCK_REGIONs are allocated in the pblock constraint related to the FCLK_CLK0.

The BUFG for this clock looks to be located at the X0Y2 clock region. This is not far from the failing clock region. Can you verify that there are no constraints that would cause the clock to be limited to where it can drive loads?

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
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Adventurer
Adventurer
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Registered: ‎12-26-2016

Re: Place 30-504 Error

It is now resolved and was a constraints problem. But there is no real solution to this topic as I can't reproduce the failing state anymore.

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