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Visitor darios_87
Visitor
717 Views
Registered: ‎04-10-2018

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair

Hello,
I have to do a design with several clocks in it.
So far I wrote a test code with only the clocking resources and some simple logic to see if I don't have problems with the clocking network.
I'm using part XC7S50-1CSGA324C and Vivado 2018.3.

The critical part is in bank15 where I have 1 single ended clock (R14) and 1 differential clock (D14 and D15), both MRCC pins.
I'm trying to connect both of them to a different MMCM. I think it is possible because 1 clock can use the MMCM in bank15 (MMCM X0Y1) and the other can use the MMCM in an adjacent clock region (like MMCM X0Y2 in bank 16)
I have another clock in bank14 using MMCM X0Y0.

I got the following error in the implementation:

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets i_trigger_clk/inst/clk_in1_trigger_clk] >

	i_trigger_clk/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X0Y74
	 i_trigger_clk/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y2

	The above error could possibly be related to other connected instances. Following is a list of 
	all the related clock rules and their respective instances.

	Clock Rule: rule_mmcm_bufg
	Status: PASS 
	Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
	 i_trigger_clk/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X0Y2
	 and i_trigger_clk/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y28

 

i_trigger_clk is an MMCM whose input clk comes from pin R14 (MRCC) which is inside IOB_X0Y74, so in the top half of the device according to ug475_7series_pkg_pinout page 36.
So vivado inferred an IBUF for it in IOB_X0Y74 (which is in bank 15 which contains MMCM X0Y1).

Being MMCM X0Y1 already used by the differential clock input, the i_trigger_clk MMCM is placed in clock region X0Y2 as I expected.

I don't understand the following:


- In the first line of the error I guess the clock-MMCM pair is IOB_X0Y74-MMCME2_ADV_X0Y2 as listed after. Why would their placement be sub-optimal?
An MRCC pin can drive "CMTs above and below" as stated in ug472_7series_clocking page 24.


- "Clock Rule: rule_mmcm_bufg": it is about the BUFG in the MMCM feedback.
This BUFG for some reason is placed in BUFGCTRL_X0Y28, which is in the bottom hald of the device, therefore violating the rule described as also stated in ug475.
But it says status PASS (???).

So what is the error here?
Connecting IOB_X0Y74 to MMCME2_ADV_X0Y2 or connecting BUFGCTRL_X0Y28 to MMCME2_ADV_X0Y2?
If the error is caused by BUFGCTRL_X0Y28, why vivado decided to place it in the bottom half and violate the rule?

(p.s. how do I know in which IOB a particular pin is located when I don't have an implemented design open?)

I'm sorry for any mistake I might have done but I'm still learning about xilinx fpga architecture.

Best regards,
Dario

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4 Replies
Xilinx Employee
Xilinx Employee
709 Views
Registered: ‎05-22-2018

Re: [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair

Hi @darios_87 ,

 

Please check this AR# link, might be helpful:

https://www.xilinx.com/support/answers/66659.html

Thanks,

Raj

 

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Xilinx Employee
Xilinx Employee
646 Views
Registered: ‎07-16-2008

回复: [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair

Here're some descriptions in UG472.

CMTs can, with limitations, drive other CMTs in the adjacent regions using the CMT backbone. Similarly, clock-capable pins can drive, with the same limitations, CMTs in adjacent regions.

If it is necessary to drive a CMT from a clock-capable input that is not in the same clock region, and there is no MMCM/PLL in the same clock region as the clock-capable input, the attribute CLOCK_DEDICATED_ROUTE = BACKBONE must be set. In this case, the MMCM or PLL do not properly align outputs to the input clock.

With regards to the MMCM-BUFG placement, it does seem to violate the clocking rule of the same top/bottom half. I'd suggest that you add CLOCK_DEDICATED_ROUTE constraint as suggested and re-implement. See how it goes.

 

> how do I know in which IOB a particular pin is located when I don't have an implemented design open?

With a design at hand, the easy way is to open a design (elaborated, synthesized or implemented) and run the following Tcl command to query the property, provided that the IO ports have been locked.

get_property LOC [get_ports <port name>]

e.g.

get_property LOC [get_ports i_trigger_clk]

 

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Visitor darios_87
Visitor
630 Views
Registered: ‎04-10-2018

回复: [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair

 

 


CMTs can, with limitations, drive other CMTs in the adjacent regions using the CMT backbone. Similarly, clock-capable pins can drive, with the same limitations, CMTs in adjacent regions.

If it is necessary to drive a CMT from a clock-capable input that is not in the same clock region, and there is no MMCM/PLL in the same clock region as the clock-capable input, the attribute CLOCK_DEDICATED_ROUTE = BACKBONE must be set. In this case, the MMCM or PLL do not properly align outputs to the input clock.


That works, thanks.

In this case, the MMCM or PLL do not properly align outputs to the input clock.

I guess this means that the clock output from the MMCM cannot be in phase with the input pin, so the 'Phase alignment' option in the wizard (that places a BUFG in the feedback) cannot be effective?

 


With regards to the MMCM-BUFG placement, it does seem to violate the clocking rule of the same top/bottom half. I'd suggest that you add CLOCK_DEDICATED_ROUTE constraint as suggested and re-implement. See how it goes.


I actually made a mistake here, BUFGCTRL_X0Y28 is in top half of the device like the clock input and the MMCM (BUFG X0Y0 to X0Y15 are in the bottom, X0Y16 to X0Y31 are in the top). I just got confused in device view, therefore there's no rule violation so 'Status: PASS' make sense.

 

Actually I found out I can even route to an MMCM in another clock region going through either a BUFG or a BUFMR+BUFR, but I guess these solution have different timing implication which I didn't investigate yet.

In the end setting the CLOCK_DEDICATED_ROUTE BACKBONE solved the problem.

Best regards,

Dario

 

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Xilinx Employee
Xilinx Employee
613 Views
Registered: ‎07-16-2008

回复: [Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair

If the MMCM is not driven by clock-capable IO (IBUFG), the MMCM will not compensate the delay of the input path.

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