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Observer
Observer
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Registered: ‎04-02-2019

[Place 30-58] IO placement is infeasible

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I am trying to implement a 32 bit booth multiplier on zybo FPGA board using XILINX vivado 2019.1. At the implementation stage i am getting warning: "[Place 30-58] IO placement is infeasible. Number of unplaced terminals (130) is greater than number of available sites (100)." can somebody tell me how to resolve this error?

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: [Place 30-58] IO placement is infeasible

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Hi @drilip 

You also could consider using the module analysis flow as mentioned i the Hierarchical Design Guide. This would only support non-project commands, but you could synthesize out of context OOC, which would not insert I/O buffers. You would need to remain in the OOC mode during implementation, either through the link_design -mode out_of_context or by just starting opt_design after an OOC synthesis. I will link OOC constraints section of Hierarchical Design Guide.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug905-vivado-hierarchical-design.pdf#page=9

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Registered: ‎06-21-2017

Re: [Place 30-58] IO placement is infeasible

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The error is telling you that you require 130 IO pins and you only have 100 available.  Do you really need 130 bits of IO?  If you do, you need a chip with more pins else you need to reduce the number of IO in your design.

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Guide
Guide
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Registered: ‎01-23-2009

Re: [Place 30-58] IO placement is infeasible

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You can't... (If this is really what you are trying to do).

Your top level module has 130 ports - presumably 2x32 bit inputs, 1x64 bit output and a clock and reset (just guessing at the last two). This is 130 ports.

The FPGA device you are using only has 128 physical pins. It doesn't fit.

So if you are planning on having this module as the top module of your design (hence ported out to the pins of the FPGA) then it won't fit. However, I doubt this is what you are really trying to do, since the Zybo board has lots of "other" things connected to its pins - it doesn't have anywhere near 130 free pins - I would suspect fewer than 16 of them are available for "general purpose" use.

If you are not really planning on actually putting the design in the Zybo board as a top level and are (for example) trying to implement a sub-module of the real design, or are just experimenting with implementing a particular architecture (and never plan to actually download it to the FPGA), then you can use "out of context (OOC)" mode. In OOC mode, the tool does not attempt to route the I/O of the top level module to the pins of the FPGA and just leaves them "dangling" inside the FPGA.

OOC mode is selected using synth_design -mode out_of_context in non-project mode, or by right clicking on the desired module in the GUI, and selecting "Set as out of context for synthesis". However you don't appear to be able to do this on a top level module in the GUI, so you will need to write some kind of wrapper outside this module so that the multiplier is a sub-module - sub-modules can be set as OOC in the GUI.

Avrum

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Observer
Observer
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Registered: ‎04-02-2019

Re: [Place 30-58] IO placement is infeasible

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Thanks avrumw,

As u mentioned, i am only trying to implement as an example to compare two different types of multipliers in terms of speed and resource utilization. I selected the design as OOC and created a wrapper but problem remains the same. 

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: [Place 30-58] IO placement is infeasible

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If your only checking, use a bigger chip,

 

Other options to thos mentioned are to use virtual IO blocks,

     these are in the IP section, and you "just" conect your entity to them, and you only "need" a clock input to the chip

       The advantage of this to you is not only the lack of pin, but the slowest part of the FPGA is the IOB pins.         Using virtual IO menas the lgic is wholey inside the FPGA and can be routed optimuly,

 

One othe thing, Vivado is clever,,,,  Not AL clever , but damend better at optimisation than I am,,,

    Vivado only runs till your timming constraints are meet, so no timing constraint, the desing could well be running slower than it could, 

   BUT, if yor constraint is to tight, then vivado will give you a worse  fit ..

 

good luck

 

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Observer
Observer
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Registered: ‎04-02-2019

Re: [Place 30-58] IO placement is infeasible

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Virtual IOs are implementable? can i perform timing analysis on my design then?.

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: [Place 30-58] IO placement is infeasible

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Yep, and the results, as not including the IOB registers, should be more reliable.

Still suggest you make your IP OOC, and instantiate that into a top level block with the virtual IO, that way your IP is differentiated.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Observer
Observer
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Registered: ‎04-02-2019

Re: [Place 30-58] IO placement is infeasible

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Can you suggest me any link or tutorial for the method you mentioned.

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: [Place 30-58] IO placement is infeasible

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No real tutorial, is "just" all "standard" IP and logic design.

for instance , this is the Virtual IO documents for vivado

https://www.xilinx.com/support/documentation/ip_documentation/vio/v2_0/pg159-vio.pdf

as you are not wanting to look at or drive the signals of you rentity, then you are not worried about how to use the JTAG connection.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Xilinx Employee
Xilinx Employee
389 Views
Registered: ‎05-08-2012

Re: [Place 30-58] IO placement is infeasible

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Hi @drilip 

You also could consider using the module analysis flow as mentioned i the Hierarchical Design Guide. This would only support non-project commands, but you could synthesize out of context OOC, which would not insert I/O buffers. You would need to remain in the OOC mode during implementation, either through the link_design -mode out_of_context or by just starting opt_design after an OOC synthesis. I will link OOC constraints section of Hierarchical Design Guide.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug905-vivado-hierarchical-design.pdf#page=9

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
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