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Participant sumaiya
Participant
150 Views
Registered: ‎10-29-2017

Place [30-60] Error

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When I tried to implement 2 PCIe RC, x2 @ gen3 one with X0Y0 and another with X0Y1. I got the following error: 


[Place 30-60] Place Check : This design requires more GTHE4_COMMON cells than are available in the target device. This design requires 2 of such cell types but only 1 compatible site is available in the target device. please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected.

Is it really incompatible to use 2 PCIe RC with different block location each in XAZU5EV-SFVC784-1Q-q? 

Please guide me how to overcome this issue?

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1 Solution

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Voyager
Voyager
87 Views
Registered: ‎10-23-2018

Re: Place [30-60] Error

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@sumaiya

It looks like you need to choose other hardware that has more resources.

PCIe
• Compliant with the PCI Express Base Specification 2.1
• Fully compliant with PCI Express transaction ordering rules
• Lane width: x1, x2, or x4 at Gen1 or Gen2 rates
• 1 Virtual Channel
• Full duplex PCIe port
• End Point and single PCIe link Root Port
• Root Port supports Enhanced Configuration Access Mechanism (ECAM), Cfg Transaction generation
• Root Port support for INTx, and MSI
• Endpoint support for MSI or MSI-X
o 1 physical function, no SR-IOV
o No relaxed or ID ordering
o Fully configurable BARs
o INTx not recommended, but can be generated
o Endpoint to support configurable target/slave apertures with address translation and Interrupt
capability

Sorry the bad news

Please mark as Solution Accepted

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Voyager
Voyager
88 Views
Registered: ‎10-23-2018

Re: Place [30-60] Error

Jump to solution

@sumaiya

It looks like you need to choose other hardware that has more resources.

PCIe
• Compliant with the PCI Express Base Specification 2.1
• Fully compliant with PCI Express transaction ordering rules
• Lane width: x1, x2, or x4 at Gen1 or Gen2 rates
• 1 Virtual Channel
• Full duplex PCIe port
• End Point and single PCIe link Root Port
• Root Port supports Enhanced Configuration Access Mechanism (ECAM), Cfg Transaction generation
• Root Port support for INTx, and MSI
• Endpoint support for MSI or MSI-X
o 1 physical function, no SR-IOV
o No relaxed or ID ordering
o Fully configurable BARs
o INTx not recommended, but can be generated
o Endpoint to support configurable target/slave apertures with address translation and Interrupt
capability

Sorry the bad news

Please mark as Solution Accepted

0 Kudos