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Visitor
Visitor
2,943 Views
Registered: ‎11-14-2017

[Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track

Hi,all

tool: vivado2016.2 FPGA: ultrascale vitrex 440

vivado placement failed due to the follow error.

Would you please help me to solve this problem? thanks very much

 

"[Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track for clock net u_tp9001_wop/u_tp9001_cor/u_snp_mac_wrp/u_DWC_gmac_top/DWC_gmac_reset_blk_inst/app_rst_blk/rst_clk_app_n_o_i in its partition defined by a rectangle from clock region X1Y3 to clock region X2Y3. A clock partition is a rectangular area covering all clock loads and the clock region for its clock root. It may cover the clock source as well. Each clock net needs to use the same routing track across all clock regions of its partition. In this case, other clock nets are already using resources in one or more clock regions of this partition.

Number of clock sources in each region:
#BUFGCE, #BUFGCTRL, #BUFGCE_DIV, #BUFG_GT
------------------------------------------------------------------------------------------------------------------------------------------------
14 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
13 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
12 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
11 | 1, 0, 0, 0 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
10 | 1, 0, 0, 0 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
9 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
8 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
7 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
6 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 6, 0, 0, 0 | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
5 | 4, 0, 0, 0 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
4 | 7, 0, 0, 0 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |24, 0, 0, 0 | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
3 | 7, 0, 0, 0 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 1, 0, 0, 0 | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
2 | 2, 0, 0, 0 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 2, 0, 0, 0 | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
1 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
0 | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
------------------------------------------------------------------------------------------------------------------------------------------------
0 1 2 3 4 5 6 7 8

Number of clock nets in each clock region of the device:
---------------------------------------------
14 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
---------------------------------------------
13 | 3 | 3 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
---------------------------------------------
12 | 3 | 3 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
---------------------------------------------
11 | 5 | 5 | 3 | 3 | 2 | 2 | 1 | 0 | 0 |
---------------------------------------------
10 | 6 | 6 | 5 | 5 | 4 | 4 | 3 | 2 | 0 |
---------------------------------------------
9 | 7 | 8 | 7 | 7 | 6 | 6 | 5 | 4 | 0 |
---------------------------------------------
8 | 11 | 12 | 11 | 11 | 10 | 11 | 10 | 7 | 1 |
---------------------------------------------
7 | 15 | 20 | 18 | 18 | 16 | 17 | 18 | 14 | 1 |
---------------------------------------------
6 | 21 | 22 | 19 | 22 | 19 | 18 | 17 | 13 | 1 |
---------------------------------------------
5 | 16 | 17 | 19 | 21 | 19 | 18 | 17 | 14 | 1 |
---------------------------------------------
4 | 17 | 23 | 22 | 21 | 19 | 17 | 16 | 13 | 1 |
---------------------------------------------
3 | 15 | 22 | 23 | 20 | 18 | 16 | 14 | 12 | 1 |
---------------------------------------------
2 | 7 | 7 | 10 | 9 | 9 | 9 | 9 | 6 | 0 |
---------------------------------------------
1 | 1 | 1 | 3 | 3 | 3 | 3 | 3 | 2 | 0 |
---------------------------------------------
0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
---------------------------------------------
0 1 2 3 4 5 6 7 8

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Scholar
Scholar
2,903 Views
Registered: ‎02-27-2008

Re: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track

Do you have any location constraints?

 

What is the usage?  The device may have run out of resources.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
Visitor
2,889 Views
Registered: ‎11-14-2017

Re: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track

this soc chip project has pin location constraints no area constraints

it looks like there is still a lot of recource not used.

the resource used list:

LUT:     35%

LUTRAM:  1%

FF:      12%

BRAM:    19%

DSP:     24%

IO       10%

BUFG     4%

MMCM     10%

 

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Moderator
Moderator
2,883 Views
Registered: ‎01-16-2013

Re: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track

@justinz,

 

Can you please share post opt dcp file? 

From the error message, tool is unable to find clock routing tracks for " Clock region X1Y3 to clock region X2Y3" 

Check the source and load of the net mentioned in error message: 

u_tp9001_wop/u_tp9001_cor/u_snp_mac_wrp/u_DWC_gmac_top/DWC_gmac_reset_blk_inst/app_rst_blk/rst_clk_app_n_o_i

 If it has any area/loc constraints then try to remove them. 

 

Clock region X7Y4 has 24 BUFGCE (24, 0, 0, 0 ). Check if you can reduce these clock buffers cells or try to move the buffers to different clock region. 

 

--Syed

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Visitor
Visitor
2,867 Views
Registered: ‎11-14-2017

Re: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track

@syedz
dcp file is attached,It's more than 300MB I will uploaded it later
there is no LOC or area constraints of u_tp9001_wop/u_tp9001_cor/u_snp_mac_wrp/u_DWC_gmac_top/DWC_gmac_reset_blk_inst/app_rst_blk/rst_clk_app_n_o_i

Clock region X7Y4 has 24 BUFGCE.How can I move the buffers to different clock region.

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Moderator
Moderator
2,855 Views
Registered: ‎01-16-2013

Re: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track

@justinz,

 

Use clock_region property. Check below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug912-vivado-properties.pdf#page=165 

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Visitor
Visitor
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Registered: ‎11-14-2017

Re: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track

@syed

     my post_opt.dcp file is more than 300MB, which is hard to be uploaded directly.

     So , here is the link of my post_opt.dcp

    link:     https://pan.baidu.com/s/1iXGavKQgvtJYI8m09byOoQ

    password :rry8

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Scholar
Scholar
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Registered: ‎08-14-2007

Re: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track

is there any solution to this issue? , I have a similar one

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track

Hi @justinz. This message would indicate that the global clocking is oversubscribed. The clock partitioner will allocate areas (rectangles) of clock regions so that a global clock can drive loads in this area.

 

These issues are typically resolved by moving or reducing clock usage, and making sure lower fanout clocks do not use too many resources. Below is an answer record with suggestions on analysis and steps to reduce clock usage.

 

https://www.xilinx.com/support/answers/67674.html

 

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