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astrome
Adventurer
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Registered: ‎04-25-2017

[Place 30-689]: Failed to place BITSLICE_CONTROL cell XCVU9P

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I got this error while designing a system for our custom board with XCVU9P FPGA part number.
 
Error message:
 
[Place 30-689] Failed to place BITSLICE_CONTROL cell TargetBoard_BIST_i/axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Tx_Nibble/Gen_1.Nibble_I_BitsliceCntrl on site BITSLICE_CONTROL_X1Y50 because Instance TargetBoard_BIST_i/axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Tx_Nibble/Gen_1.Nibble_I_BitsliceCntrl can not be placed in CONTROL of site BITSLICE_CONTROL_X1Y50 because the bel is occupied by TargetBoard_BIST_i/axi_ethernet_0/inst/pcs_pma/inst/pcs_pma_block_i/gen_io_logic/BaseX_Byte_I_Rx_Nibble/Gen_1.Nibble_I_BitsliceCntrl(port:). This could be caused by bel constraint conflict. Please check if the cell is used correctly in the design.
 
I am using a 1G/2.5G AXI ethernet subsystem here in my design (axi_ethernet_0). Kindly check and revert with possible solution.
 
Thanks & Regards.
 
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marcb
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Registered: ‎05-08-2012

Hi @astrome 

This type of message (Failed to plae <> because instance <> can not be placed in <> because the bel is occupied.." would mean there is a constraints conflict. I suspect thta the IP is setting constraints on either the BITSLICE or the top-level port it is connected to. The conflicting part would be if are either setting BITSLICE or port LOC constraints. I would check the IO constraints connected to the IP.

Most IPs will allow to customize IO or GT placement. You would either need to customize the IP to use the desired IO or comment out the IP constraints (nor recomended)


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marcb
Moderator
Moderator
2,337 Views
Registered: ‎05-08-2012

Hi @astrome 

This type of message (Failed to plae <> because instance <> can not be placed in <> because the bel is occupied.." would mean there is a constraints conflict. I suspect thta the IP is setting constraints on either the BITSLICE or the top-level port it is connected to. The conflicting part would be if are either setting BITSLICE or port LOC constraints. I would check the IO constraints connected to the IP.

Most IPs will allow to customize IO or GT placement. You would either need to customize the IP to use the desired IO or comment out the IP constraints (nor recomended)


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------

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astrome
Adventurer
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Registered: ‎04-25-2017

Thank you @marcb . There was a problem with the hardware pins.

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mik3l3_hdl
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Registered: ‎08-15-2019

Hi @astrome ,

 

i got a similar problem when designing an interface to connect my Ultrascale XCVU9P to a DAC board.

 

[Place 30-689] Failed to place BITSLICE_CONTROL cell dacInterface/dataClockOut/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[7].bs_ctrl_inst on site BITSLICE_CONTROL_X0Y15 because Instance dacInterface/dataClockOut/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[7].bs_ctrl_inst can not be placed in CONTROL of site BITSLICE_CONTROL_X0Y15 because the bel is occupied by dacInterface/ABOut/inst/top_inst/bs_ctrl_top_inst/BITSLICE_CTRL[7].bs_ctrl_inst(port:). This could be caused by bel constraint conflict. Please check if the cell is used correctly in the design.

 

 

Could you please give me any hints on how to fix this. I read the previous messages but I am still lost.

 

Thanks

Regards

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