03-19-2018 08:43 PM - edited 03-19-2018 09:15 PM
We are getting an implementation critical warning w.r.t. the MISO or Io1_i pin of the axi_quad_spi core. The issue arises because the core expects the input port to be placed in an IOB. This is also stated in the supporting product documentation. Unfortunately, we are not in a position to have the input as part of an IOB. This is because the input to the SPI in our design can be sourced is from 2 separate devices, via a multiplexer, ie.
assign SPI0_MISO = DEVCE_1_CS == 1'b0)?DEVICE_1_MISO: DEVICE_2_MISO;
One of these devices outputs, DEVICE_1_MISO, is provided by internal FPGA logic.
Is it possible to alter the property IOB=TRUE for this input pin of the axi_quad_spi? If yes, I would be grateful if someone would explain how it is changed.
03-22-2018 09:32 PM
Hi @wmaguire. You can override this constraint by adding another IOB constraint on the same register cell, with the value of "FALSE". With constraint precedence, The last constraint will be applied, so you would only need to make sure that it is last in the processing order.
set_property IOB FALSE [get_cells IO1_I_REG]
03-27-2018 09:39 PM
04-12-2018 07:27 PM
Apologies for not getting back sooner. I have been working on a different project and was not checking the forum. I will try your suggestion and report the results once I get some time to look at it again.
04-17-2018 04:55 AM
Can you provide any update on this thread?