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Visitor
Visitor
8,630 Views
Registered: ‎06-15-2016

[Place 30-99] Placer failed with error: 'Failed to commit FFs'

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[Place 30-99] Placer failed with error: 'Failed to commit FFs'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

 

I don't understand why I am getting this error on compile. There are no additional errors, the critical warnings have not changed from my previous build, and there are about 5717 Warning messages. 

 

This error is very vague and I cannot get any information from it. What does it mean?

 

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Xilinx Employee
Xilinx Employee
8,625 Views
Registered: ‎02-14-2014

Hello @cpagravel,

 

Did you check runme.log file present in synth_1 and impl_1 folder to see if you can get some clue about these errors? Can you share these files here?

Regards,
Ashish
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

https://forums.xilinx.com/t5/7-Series-FPGAs/Place-30-99-Errors-in-Place-Design/td-p/339013
Thanks and Regards
Balkrishan
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Visitor
Visitor
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Registered: ‎06-15-2016

I did not check those files. I will look at them now. Here they are attached.

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Visitor
Visitor
8,613 Views
Registered: ‎06-15-2016

I think this is unrelated. My design has nothing wrong with the BUFG usage. I got a successful build, and then made some very minor changes and it failed this time around.
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Moderator
Moderator
8,612 Views
Registered: ‎07-01-2015

Hi @cpagravel,

 

I have seen this issue while migrating from ISE to Vivado.

If so please verify if LOCK_PINS property is set on the FF.

 

Also see if there are any location constraints set which may not allow this FF to place.

If possible please try once in latest version of the tool.

Thanks,
Arpan
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Visitor
Visitor
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Registered: ‎06-15-2016

Hi @arnpansur,

I am using Vivado 2016.2. I am particularly confused about this because I had produced a successful build yesterday, but after removing some unused signals, the build failled. I thought Vivado had no randomness in the success of its builds. Perhaps, I overlooked something though.
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Moderator
Moderator
8,376 Views
Registered: ‎01-16-2013

@cpagravel

 

Can you recheck if the signals removed are unused signals only? Unless the design files are changes it is expected from vivado to always show consistent and same results. 

 

Is it possible to share the post opt dcp file?

 

Regards,

Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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