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Visitor jys_ee
Visitor
1,439 Views
Registered: ‎12-13-2017

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'

 This is the full messages: 

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

This error is quite vague and I don't know how to resolve it.

Here are runme.log file present in synth_1 and impl_1 folder.

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3 Replies
Moderator
Moderator
1,421 Views
Registered: ‎01-16-2013

Re: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'

@jys_ee

 

The error message itself has the resolution... Did you try/check the resolution?

ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PIXCLK_IBUF] >

PIXCLK_IBUF_inst (IBUF.O) is locked to IOB_X0Y170
PIXCLK_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
Resolution: Poor placement of an IO pin and a BUFG has resulted in the router using a non-dedicated path between the two. There are several things that could trigger this DRC, each of which can cause unpredictable clock insertion delays that result in poor timing. This DRC could be caused by any of the following: (a) a clock port was placed on a pin that is not a CCIO-pin (b)the BUFG has not been placed in the same half of the device or SLR as the CCIO-pin (c) a single ended clock has been placed on the N-Side of a differential pair CCIO-pin.

 

From the log file, I see that you are using "xc7z035ffg676-1" device and the IO "PIXCLK_IBUF_inst" locked to IOB_X0Y170 is not Clock capable IO (CCIO). 

Capture.JPG

 

You either need to change the IO to clock capable site or use the following constraint in XDC: 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PIXCLK_IBUF]

 

Check the following link. IO which has pin name SRCC or MRCC are clock capable IO. 

https://www.xilinx.com/support/packagefiles/z7packages/xc7z035ffg676pkg.txt

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Visitor jys_ee
Visitor
1,402 Views
Registered: ‎12-13-2017

Re: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'

I've tried writing set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PIXCLK_IBUF] in .xdc file, but the error still exist.

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Moderator
Moderator
1,395 Views
Registered: ‎01-16-2013

Re: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'

@jys_ee,

 

Is it not possible to use CCIO pin? Did you rerun the implementation? Also check if your CLOCK_DEDICATE_ROUTE constraint is being picked by tool.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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