Place:543 error problem

ninjamafiakhan3 · ‎06-21-2012

(Windows 7 32-bit, Ultimate Edition, ISE 12.4, Spartan 3-A DSP 3400A, cs484, grade -4)

I get the following messages in the MAP report:

Section 1 - Errors
------------------
ERROR:Place:543 - This design does not fit into the number of slices available
   in this device due to the complexity of the design and/or constraints.

   Unplaced instances by type:

     DSP48A    21 (16.8)

   Please evaluate the following:

   - If there are user-defined constraints or area groups:
     Please look at the "User-defined constraints" section below to determine
     what constraints might be impacting the fitting of this design.
     Evaluate if they can be moved, removed or resized to allow for fitting.
     Verify that they do not overlap or conflict with clock region restrictions.
     See the clock region reports in the MAP log file (*map) for more details
     on clock region usage.

   - If there is difficulty in placing FFs:
     Evaluate the number and configuration of the control sets in your design.

   The following instances are the last set of instances that failed to place:

   0. Placer RPM "Lut Ram" (size: 21)
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000019
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000002d
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000002c
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000002b
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000002a
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000029
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000028
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000027
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000026
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000025
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000024
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000023
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000022
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000021
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000020
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000001f
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000001e
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000001d
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000001c
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000001b
      DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000001a

   These instances could be impacted by the following constraints
   (the line IDs below correspond with the instances above):

   Clock Region restrictions

   0. DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000019
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000002d
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000002c
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000002b
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000002a
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000029
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000028
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000027
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000026
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000025
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000024
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000023
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000022
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000021
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk00000020
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000001f
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000001e
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000001d
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000001c
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000001b
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
   DSP48A
   IF_ddc_inst0/instance_name/basebandsampling_ddc_matlab2010_x0/cfir1_73b633e
   cfd/fir_compiler_v3_2/comp0.core_instance0/blk00000003/blk0000001a
        driver: GCLK ADC_CKO_buff_BUFG @ BUFGMUX_X2Y10
        CLOCKREGION_X1Y0
ERROR:Place:120 - There were not enough sites to place all selected components.
   Some of these failures can be circumvented by using an alternate algorithm
   (though it may take longer run time). If you would like to enable this
   algorithm please set the environment variable XIL_PAR_ENABLE_LEGALIZER to 1
   and try again 


ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

My questions and observations:

The output of BUFGMUX X2Y10 connects to global clock lines, so why would the use of this BUFGMUX hinder the placement of the DSP48 blocks? Unless the hindrance is due to some other constraint, in which case it is not reported in the detailed MAP reprt.

I have tried forcing the BUFGMUX for this clock to be at X2Y11, not forcing its location at all (letting the tools decide for themselves), using CLOCK_DEDICATED_ROUTE = FALSE for the clock to the DDC, infering a DCM, and removing all instance placement constraints from my design. With the exception of one implementation run, all runs fail at the MAP stage, with the EXACT same error message (showing that BUFGMUX is constrained to be at X2Y10, which I don't force it to be and sometimes prohibit). The one run which went past the MAP stage placed and routed with 0 score and the resulting bitstream is currently working fine. The error seems to occur randomly. I tried Project file clean-up, manual deletion of leftover files, creation of a new project. Nothing worked. I also tried setting XIL_PAR_ENABLE_LEGALIZER to 1 (which caused the report to stop suggesting the setting of this environment variable as a possible work-around, but the error messages remained the same) and changing the Starting Placer Cost Table from 1 to 2, to no avail.

I feel that the messages are not telling me enough to find the cause of my problem. I know that placement is not impossible, as the design placed and routed well once before. Also, I can't find a section titled "clock region report" in .map or .mrp file. The Generate Detailed MAP Report option is set. I hope anyone will shed some light on this. Thanks for reading.

bwade · ‎06-21-2012

Your are having fitting issues with the DSP48A instances mentioned in the error message. Since you have removed all user constraints, the limitations on the DSP48A placement are coming from the clock placer which needs to floorplan the design so that no more than eight global clocks have loads in any one clock region. There are also potential conflicts between side and top/bottom BUFGs to consider. Since you have a successful placement, it's possible to leverage that successful floorplan and convert it to user constraints so that it is locked in permanently. For most architectures, the map report (.map) provides the constraints needed to do this, but if I'm not mistaken, they do not for S3A and so it is necessary to do this manually. Load the design into FPGA Editor and for each BUFG output net, define an area group with a range equivalent to what you see being used in the editor:

NET "clk1" TNM_NET = "TNM_clk1" ;
TIMEGRP "TNM_clk1" AREA_GROUP = "AG_clk1" ;
AREA_GROUP "AG_clk1" RANGE = CLOCKREGION_X0Y0, CLOCKREGION_X0Y1;

You can then tweak that floorplan manually if you think any of the clock domains need more clock regions as long as you don't constrain more than eight clocks to one region or create conflicts with side BUFGs. Check the user guide for the side BUFG restrictions. Your goal will be to allocate more clock regions to the clock(s) driving the DSP48As. To do this, it may be necessary to take some clock regions away from other clock domains that don't really need them.

DSP48A placement is also complicated by the need to align cascade chains into a single column. It may be necessary to also lock down the DSP48A based on the successful placement.