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Visitor
Visitor
15,050 Views
Registered: ‎05-07-2014

Place design error: [Place 30-719]

During placement I get the following error from Vivado, but I can't decipher what is causing the problem. A little help, please?

 

     [Place 30-719] Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair.

 

The target is a Virtex 7 V2000T with 1925 pins.

 

Thanks!

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Xilinx Employee
Xilinx Employee
15,042 Views
Registered: ‎11-28-2007

Hi Getz53,

 

I'm not familiar with that error message and can't find any answer record on it, although I find it already quite descriptive and indicating what the issue is.

 

Is this the full error or does it also tell which IO pin IDELAY BUFG is involved?

How many BUFGs are in your design?

 

Have you taken a look at the Ultrafast methodology guide and the section: Additional Clocking Considerations for SSI Devices

screenshot_001.jpg

 

If I were you, I would try to visualize the problem using the following method:

1) open the synthesized design

2) run "opt_design" in the Tcl console

3) run "place_ports" - yes, not place_design. This will place ports AND the clocks and should reproduce the error you saw with the difference that it should remain in memory for you to analyze why there is a problem.

 

It might be necessary to lock down all BUFGs using LOC property constraints.

 

 

Best regards,

Dries

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Visitor
Visitor
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Registered: ‎05-07-2014

Thanks for your reponse, Driesd.

 

There are two problems here. First, I am new to Xilinx. Second, this is someone else's design, so I am not that familiar with it.

 

Here is the entire error message. My first inclination is that there is a constraint somewhere that manually places the BUFGs and violates the referenced clock rule, but I don't know where to look. I don't see a reference to a pin:

 

[Place 30-719] Sub-optimal placement for a global clock-capable IO pin-IDELAY-BUFG pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.


 < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets goliath_top/lsi/dps/dram_phy/gen_dq[0].dbyte_inst/O854] >

 

 goliath_top/lsi/dps/dram_phy/gen_dq[0].dbyte_inst/idelay_inst (IDELAYE2.DATAOUT) is locked to IDELAY_X0Y594(SLR 3)


  iddr_inst_i_1__2 (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y127 (in SLR 3)

 The above error could possibly be related to other connected instances. Following is a list of
 all the related clock rules and their respective instances.

 

 Clock Rule: rule_multi_slr_bufg
 Status: PASS
 Rule Description: For a multi-SLR device, a maximum of one BUFG at same relative position in different
 SLRs can be used, that is two BUFG sites  whose Y-index differs by a multiple of 32 cannot be used
 at the same time and iddr_inst_i_1__2 (BUFG.O) is provisionally placed by clockplacer on BUFGCTRL_X0Y127 (in SLR 3)

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Hi,

 

Open synthesized design and search for the cell " goliath_top/lsi/dps/dram_phy/gen_dq[0].dbyte_inst/idelay_inst".

 

Track to the port connected to the IDATAIN pin of this IDELAY. See if this port it is locked to CCIO pin.

 

I have seen this error in one case where the port connected to IDATAIN is not locked to a CCIO pin.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
15,007 Views
Registered: ‎11-28-2007

Hi Getz53,

 

If you're new to Xilinx, you can give it a try, but the 2000T is really advanced. I would seek help directly from where you got the design.

 

Anyway, if there are any existing BUFG LOC constraints on this clock, I would try once and remove them.

Maybe it was incorrect and not up to date anymore...

 

 

Best regards

Dries

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Visitor
Visitor
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Registered: ‎05-07-2014

I am not a newbie to FPGAs, just to Xilinx.   :)

 

Attached is a diagram of the circuit that is causing the error. The diagram is taken from the synthesis view of the logic.

 

The IDELAYE2 block is at the left of the diagram. It's IDATAIN input is driven by an IBUFDS block which does not appear in the RTL so I assume it was added by synthesis. The two inputs of the IBUFDS block are fed by the two outputs of a OBUFTDS block. Those IBUFTDS outputs also go to output pins sbdqs and sbdqsn. The DATAOUT output of the IDELAYE2 block drives a BUFG (not shown) which ten drives the clock inputs of some registers.

 

Does this provide any useful information? Is there something else that would be helpful?

 

Thanks.

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Visitor
Visitor
14,997 Views
Registered: ‎05-07-2014

Sorry, I didn't click Add Attachment before I clicked Post

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Visitor
Visitor
14,996 Views
Registered: ‎05-07-2014

Hmmm. I still don't see the attachment. Does anyone else?

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Xilinx Employee
Xilinx Employee
14,987 Views
Registered: ‎09-20-2012

Hi,

 

I dont see the attachment. Can you archive it and attach?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Scholar
Scholar
14,979 Views
Registered: ‎07-01-2008

It sounds like you have a delay element in your clock path. Is that intended?

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