Place error for GTH PLL

[amitra2015]

Hi,

I am getting the following place error for GTH QPLL. It seems that due to one of my constraints the placement of QPLL is getting locked to one bank while some other constraint is trying to provisionally place it to some other bank.

It will be helpful if someone helps me to fix my constraint file to overcome this error. I have pasted the error message as well as the constraint file below.

One confusion is different clock rules are shown to be PASSed. Still the placement is failing:

*****************************************************

[Place 30-510] Unroutable Placement! A GTHE_COMMON / GTHE_CHANNEL clock component pair is not placed in a routable site pair. The GTHE_COMMON component can use the dedicated path between the GTHE_COMMON and the GTHE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sgmii_port_0/U0/core_gt_common_i/gt0_qplloutclk_out] >

    sgmii_port_0/U0/core_gt_common_i/gthe2_common_i (GTHE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y8
     sgmii_port_1/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y39
     sgmii_port_3/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y35
     sgmii_port_4/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y28
     sgmii_port_2/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y32
     sgmii_port_0/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i (GTHE2_CHANNEL.QPLLCLK) is locked to GTHE2_CHANNEL_X1Y36

    The above error could possibly be related to other connected instances. Following is a list of
    all the related clock rules and their respective instances.

    Clock Rule: rule_bufds_bufg
    Status: PASS
    Rule Description: A BUFDS driving a BUFG must be placed on the same half side (top/bottom) of the device
     sgmii_port_0/U0/core_clocking_i/ibufds_gtrefclk (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X1Y17
     sgmii_port_0/U0/core_clocking_i/bufg_gtrefclk (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

    Clock Rule: rule_bufds_gthchannel_intelligent_pin
    Status: PASS
    Rule Description: A BUFDS driving a GTHChannel must both be placed in the same or adjacent clock region
    (top/bottom)
     sgmii_port_0/U0/core_clocking_i/ibufds_gtrefclk (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X1Y17
     sgmii_port_1/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i (GTHE2_CHANNEL.GTREFCLK0) is locked to GTHE2_CHANNEL_X1Y39
     sgmii_port_3/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i (GTHE2_CHANNEL.GTREFCLK0) is locked to GTHE2_CHANNEL_X1Y35
     sgmii_port_4/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i (GTHE2_CHANNEL.GTREFCLK0) is locked to GTHE2_CHANNEL_X1Y28
     sgmii_port_2/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i (GTHE2_CHANNEL.GTREFCLK0) is locked to GTHE2_CHANNEL_X1Y32
     sgmii_port_0/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i (GTHE2_CHANNEL.GTREFCLK0) is locked to GTHE2_CHANNEL_X1Y36

    Clock Rule: rule_bufds_gthcommon_intelligent_pin
    Status: PASS
    Rule Description: A BUFDS driving a GTHCommon must both be placed in the same or adjacent clock region
    (top/bottom)
     sgmii_port_0/U0/core_clocking_i/ibufds_gtrefclk (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X1Y17
     sgmii_port_0/U0/core_gt_common_i/gthe2_common_i (GTHE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on GTHE2_COMMON_X1Y8

    Clock Rule: rule_gt_bufg
    Status: PASS
    Rule Description: A GT driving a BUFG must be placed on the same half side (top/bottom) of the device
     sgmii_port_0/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i (GTHE2_CHANNEL.RXOUTCLK) is locked to GTHE2_CHANNEL_X1Y36
     and sgmii_port_0/U0/core_clocking_i/rxrecclkbufg (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y30

*****************************************************

Constraint file xdc:

create_clock -period 40.000 -name clk -waveform {0.000 20.000} [get_ports clk]
create_clock -period 8.000 -name clk125M_p -waveform {0.000 4.000} [get_ports clk125M_p]
create_generated_clock -name sgmii_port_0/U0/pcs_pma_block_i/sgmii_logic/clock_generation/sgmii_clk_f -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_0/U0/pcs_pma_block_i/sgmii_logic/clock_generation/sgmii_clk_f_reg/Q]
create_generated_clock -name sgmii_port_0/U0/pcs_pma_block_i/sgmii_logic/clock_generation/sgmii_clk_r -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_0/U0/pcs_pma_block_i/sgmii_logic/clock_generation/sgmii_clk_r_reg/Q]
create_generated_clock -name sgmii_port_1/U0/sgmii_logic/clock_generation/sgmii_clk_f -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_1/U0/sgmii_logic/clock_generation/sgmii_clk_f_reg/Q]
create_generated_clock -name sgmii_port_1/U0/sgmii_logic/clock_generation/sgmii_clk_r -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_1/U0/sgmii_logic/clock_generation/sgmii_clk_r_reg/Q]
create_generated_clock -name sgmii_port_2/U0/sgmii_logic/clock_generation/sgmii_clk_f -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_2/U0/sgmii_logic/clock_generation/sgmii_clk_f_reg/Q]
create_generated_clock -name sgmii_port_2/U0/sgmii_logic/clock_generation/sgmii_clk_r -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_2/U0/sgmii_logic/clock_generation/sgmii_clk_r_reg/Q]
create_generated_clock -name sgmii_port_3/U0/sgmii_logic/clock_generation/sgmii_clk_f -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_3/U0/sgmii_logic/clock_generation/sgmii_clk_f_reg/Q]
create_generated_clock -name sgmii_port_3/U0/sgmii_logic/clock_generation/sgmii_clk_r -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_3/U0/sgmii_logic/clock_generation/sgmii_clk_r_reg/Q]
create_generated_clock -name sgmii_port_4/U0/sgmii_logic/clock_generation/sgmii_clk_f -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_4/U0/sgmii_logic/clock_generation/sgmii_clk_f_reg/Q]
create_generated_clock -name sgmii_port_4/U0/sgmii_logic/clock_generation/sgmii_clk_r -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_4/U0/sgmii_logic/clock_generation/sgmii_clk_r_reg/Q]

set_property PACKAGE_PIN G10 [get_ports clk125M_p]
set_property PACKAGE_PIN D8 [get_ports rxp_0]
set_property PACKAGE_PIN A6 [get_ports rxp_1]
set_property PACKAGE_PIN H8 [get_ports rxp_2]
set_property PACKAGE_PIN E6 [get_ports rxp_3]
set_property PACKAGE_PIN P8 [get_ports rxp_4]
set_property PACKAGE_PIN P36 [get_ports mdc_ext_gtd_0_1]
set_property PACKAGE_PIN P37 [get_ports mdc_ext_gtd_2]
set_property PACKAGE_PIN T41 [get_ports mdc_ext_gtd_3_4]
set_property PACKAGE_PIN R33 [get_ports MDIO]

Thanks and regards,

[vemulad]

Hi @amitra2015

Which device are you using?

Thanks,

Deepika.

[amitra2015]

Hi,
I am using Virtex7vx690tffg 1761 - 2

[vemulad]

Hi @amitra2015

Please see below for the clock region of the GT_CHANNEL sites mentioned in the error.

site -- clock region

GTHE2_CHANNEL_X1Y39 -- X1Y9

GTHE2_CHANNEL_X1Y35 -- X1Y8

GTHE2_CHANNEL_X1Y28 -- X1Y7

GTHE2_CHANNEL_X1Y32 -- X1Y8

GTHE2_CHANNEL_X1Y36 -- X1Y9

All GTHE2_CHANNEL instances connected to the same GTHE2_COMMON instance should be placed in single clock region.

If you are using 7 series transcievers wizard IP then regenerate the IP by selecting correct GTHE2_CHANNEL locations.

Thanks,

Deepika.

[amitra2015]

Hi Deepika,

Can you please refer me to the link or document where you could map the GT_CHANNEL sites with the corresponding clock region as mentioned in your reply.

What I understood that during regeneration of the IP, I have to force the placement of the site (e.g. X1Y39) to the correct clock region (X1Y9). Is it possible to do manually in xdc? Or, the only way out is to regenerate the IP using the transceiver wizard?

Thanks and regards,

Amitra

[vemulad]

Hi @amitra2015

You can open synthesized design to know the clock region of GT_CHANNEL sites. Just search for desired GTHE2_CHANNEL site in device view and check the site properties to know the clock region.

The placement of the GT_CHANNEL instances depends up on the locations of MGTRXP/MGTTXP pins. Refer to package placement diagram at page-403 of http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf

If you cannot change the MGTRXP/MGTTXP locations then you need to regenerate the IP with desired locations.

Thanks,

Deepika.

[yenigal]

Hi

The SGMII IP core generation for 7 series doesn't give an option to select the GT Location in the GUI and need to be done in the top level XDC.

You can assign the transciver pins to the same quad from the below pin mapping in your top xdc

http://www.xilinx.com/support/packagefiles/v7packages/xc7vx690tffg1761pkg.txt

Or constrain the GT channels from the device view directly that belong to the same quad

Below is the sample constraint from the sgmii example design

set_property LOC GTHE2_CHANNEL_X1Y39 [get_cells */*/*/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gthe2_i]

The SGMII IP core generation for 7 series doesn't give an option to select the GT Location in the GUI and need to be done in the top level XDC.

[amitra2015]

Hi Satish,

I tried with the xdc constraint you provided but, even after adding that and synthesizing, I can see that the clock regions are locked to the same corresponding areas (as mentioned in Deepika's reply) and as a result I am getting the same implementation error.

What I understood from the constraint is, irrespective of the SGMII GTH channel number I am using (0..4), the clock regions will be common and same as the clock region residing in the X1Y39 tile. Please let me know if I am wrong here.

Regards,

Amitra

[yenigal]

Hi

Can you copy the modified constraints you have used.

Did you lock 4 channels to the same quad.

How are you generating the cores,did you generate single core with shared logic in core and remaining 3 cores with shared logic in example design option.

PG047 has more details about the shared logic and clock sharing between multiple core targetting single quad.

[vemulad]

Hi @amitra2015

If you are directly locking the GTHE2_CHANNEL instances to a single clock region using the command below, then remove the LOC constraints on RXP/TXP pins.

set_property LOC site_name [get_cells cell_name]

If you have both RXP/TXP constraints and GT_CHANNEL constraints, the constraints which are at the end of XDC will take preceedence.

Thanks,

Deepika.

[amitra2015]

Hi,

The pins are already locked since customer has designed the board already. I tried with keeping the LOC constraints below the pin constraints in the xdc file and got the following warning after synthesis completed. I am not sure now, how can I lock the pins and set the clock regions to a particular tile simultaneously:

 [Vivado 12-1410] Cannot set LOC property of instances, Instance sgmii_port_2/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i can not be placed in GTHE2_CHANNEL of site GTHE2_CHANNEL_X1Y39 because the bel is occupied by sgmii_port_1/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gthe2_i. This could be caused by bel constraint conflict [/home/idcvalteam/mcqueen/mqn_soc/grlib-gpl-1.4.1-b4156_mqn_synth/designs/leon3-minimal/vivado/leon_mqn/leon_mqn.srcs/constrs_1/new/io.xdc:28]
Resolution: When using BEL constraints, ensure the BEL constraints are defined before the LOC constraints to avoid conflicts at a given site.

*********************************************************************

Here is my constraint file:

set_property IOSTANDARD LVCMOS18 [get_ports RsRx]
set_property IOSTANDARD LVCMOS18 [get_ports RsTx]

create_clock -period 40.000 -name clk -waveform {0.000 20.000} [get_ports clk]
create_clock -period 8.000 -name clk125M_p -waveform {0.000 4.000} [get_ports clk125M_p]
create_generated_clock -name sgmii_port_0/U0/pcs_pma_block_i/sgmii_logic/clock_generation/sgmii_clk_f -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_0/U0/pcs_pma_block_i/sgmii_logic/clock_generation/sgmii_clk_f_reg/Q]
create_generated_clock -name sgmii_port_0/U0/pcs_pma_block_i/sgmii_logic/clock_generation/sgmii_clk_r -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_0/U0/pcs_pma_block_i/sgmii_logic/clock_generation/sgmii_clk_r_reg/Q]
create_generated_clock -name sgmii_port_1/U0/sgmii_logic/clock_generation/sgmii_clk_f -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_1/U0/sgmii_logic/clock_generation/sgmii_clk_f_reg/Q]
create_generated_clock -name sgmii_port_1/U0/sgmii_logic/clock_generation/sgmii_clk_r -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_1/U0/sgmii_logic/clock_generation/sgmii_clk_r_reg/Q]
create_generated_clock -name sgmii_port_2/U0/sgmii_logic/clock_generation/sgmii_clk_f -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_2/U0/sgmii_logic/clock_generation/sgmii_clk_f_reg/Q]
create_generated_clock -name sgmii_port_2/U0/sgmii_logic/clock_generation/sgmii_clk_r -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_2/U0/sgmii_logic/clock_generation/sgmii_clk_r_reg/Q]
create_generated_clock -name sgmii_port_3/U0/sgmii_logic/clock_generation/sgmii_clk_f -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_3/U0/sgmii_logic/clock_generation/sgmii_clk_f_reg/Q]
create_generated_clock -name sgmii_port_3/U0/sgmii_logic/clock_generation/sgmii_clk_r -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_3/U0/sgmii_logic/clock_generation/sgmii_clk_r_reg/Q]
create_generated_clock -name sgmii_port_4/U0/sgmii_logic/clock_generation/sgmii_clk_f -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_4/U0/sgmii_logic/clock_generation/sgmii_clk_f_reg/Q]
create_generated_clock -name sgmii_port_4/U0/sgmii_logic/clock_generation/sgmii_clk_r -source [get_pins sgmii_port_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0] -divide_by 1 [get_pins sgmii_port_4/U0/sgmii_logic/clock_generation/sgmii_clk_r_reg/Q]

set_property PACKAGE_PIN G10 [get_ports clk125M_p]
set_property PACKAGE_PIN D8 [get_ports rxp_0]
set_property PACKAGE_PIN A6 [get_ports rxp_1]
set_property PACKAGE_PIN H8 [get_ports rxp_2]
set_property PACKAGE_PIN E6 [get_ports rxp_3]
set_property PACKAGE_PIN P8 [get_ports rxp_4]
set_property PACKAGE_PIN P36 [get_ports mdc_ext_gtd_0_1]
set_property PACKAGE_PIN P37 [get_ports mdc_ext_gtd_2]
set_property PACKAGE_PIN T41 [get_ports mdc_ext_gtd_3_4]
set_property PACKAGE_PIN R33 [get_ports MDIO]

I added this line here at the end of file:
set_property LOC GTHE2_CHANNEL_X1Y39 [get_cells sgmii_port_*/*/transceiver_inst/gtwizard_inst/*/gtwizard_i/gt0_GTWIZARD_i/gthe2_i]

*************************************************

[vemulad]

Hi @amitra2015

How many SGMII cores are present in your design?

Can you attach the IP XCI files here?

Thanks,

Deepika.

[amitra2015]

Hi Deepika,

I am using 5 instances of the SGMII core. I have attached the generated xci files for SGMII.

Regards,

Amitra

[vemulad]

Hi @amitra2015

What are the instance names of sgmii_ip.xci in your design?

I see that you have selected "shared logic in example design" for this IP. You may try choosing "shared logic in core" for this IP and regenerate it.

Thanks,

Deepika.

[amitra2015]

Hi Deepika,

Following the section named "Clock Sharing Across Multiple Cores with Transceivers" of the below PDF, the design has two xci files. One with shared logic realized in core and other instantiations are shared logic realized in example design. The clock outputs from the core realization is driving the clocks to the example design realization(s). I shared both the xci files in my previous reply.

PDF: http://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v15_0/pg047-gig-eth-pcs-pma.pdf

However, I was able to resolve the issue. The issue was with QPLLOUTCLK signals for the example design realizations. They were not being used in the design and were therefore required to be tied to '0'. Otherwise due to pin placement across different quads, placement error was coming because the GT Common will also be placed across different sites for the transceivers. That is what my understanding is.

Thank you and Satish for your continuous support.

Regards,

Amitra

[venkata]

One QPLL in a Virtex-7 device can only drive the GT channels of the same quad. From the error message, the GT locations are targeted to 5 different quads. This is not possible use case.

If you are trying to use 5 instances of SGMII targeted to 5 different quads, you will need to have 5 QPLL instances. So all the 5 instances has to chose "Shared logic in core" (or)

drive QPLL ports with a different IP configured with "Shared logic in core" option. With this option, the assumption is that the other IP also provides the QPLL clocks with same frequency value.

[vagrawal2]

In this case, if you have 5 instances of "Shared logic in core", but want to share a single reference clock with all 5 quads, how would you connect that up?

[syedz]

@vagrawal2

For better visibility and responses, can you create a new thread for your query?

--Syed