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Visitor leepoult
Visitor
383 Views
Registered: ‎01-29-2019

Placement Error [Place 30-678]

I got and error message during the "Global Placement" phase.

What can I do to avoid this problem?

And what is the main reason of this problem?

ERROR: [Place 30-678] Failed to do clock region partitioning: Cannot find an available clock routing track for clock net xxx/TIE/TIE_Regfile_V512R/TIE_Regfile_V512R_bank0/iG2_wr0_we_C2_CLK/i0/i1/xtout_uclk_5 in its partition defined by a rectangle from clock region X0Y7 to clock region X0Y7. A clock partition is a rectangular area covering all clock loads and the clock region for its clock root. It may cover the clock source as well. Each clock net needs to use the same routing track across all clock regions of its partition. In this case, other clock nets are already using resources in one or more clock regions of this partition.

 

Synthesis tool: protocompiler(from Synopsys)

P&R tool: Vivado 2018.1

Device: XCVU440-FLGA2892-2-e

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3 Replies
Xilinx Employee
Xilinx Employee
338 Views
Registered: ‎05-08-2012

Re: Placement Error [Place 30-678]

Hi @leepoult 

Can you try taking the post-opt_design version of the design and running the following commands, and attach the results?

place_ports; report_clock_utilization -file clk_util.rpt

This appears to be a GT clock, but only occupies one clock region. The report should give you a list of other clocks using this clock region. If other clocks are found to use too many clock regions, you could try using the CLOCK_LOW_FANOUT constraint. More suggestions can be found in the below AR.

https://www.xilinx.com/support/answers/67674.html


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Visitor leepoult
Visitor
325 Views
Registered: ‎01-29-2019

Re: Placement Error [Place 30-678]

Thank you for your answer!!

But I alreay retry using block assignment constraint such as "pblock".

My design use two VU440, and they are connected each others.

I moved some part of my design to another FPGA and it works fine.

 

I think we must carefully divide our large design into a couple of FPGAs.

Also I should carefully assign a block into a specific SLR (in a VU440).

Could you give some tips to do it?

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Xilinx Employee
Xilinx Employee
291 Views
Registered: ‎05-08-2012

Re: Placement Error [Place 30-678]

Hi @leepoult 

There are several suggestions on design considerations and flooplanning within the UltraFast methodology Guide (UG949). Specifically, the "Designing with SSI Devices" section linked below.

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug949-vivado-design-methodology.pdf#page=25


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