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Observer tinghao780609
Observer
199 Views
Registered: ‎12-09-2018

Placement Error [Place 30-864]

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Hi all

I got a promblem in PCIe tandem features.

[Place 30-864] Super Long Lines (SLLs) capacity is violated between Super Logic Regions (SLR): 1 and SLR: 2 for PBlock: xdma_0_i_inst_pcie4_ip_i_inst_xdma_0_pcie4_ip_Stage1_main. SLLs required = 1, SLLs available = 0.
[Place 30-864] Super Long Lines (SLLs) capacity is violated between Super Logic Regions (SLR): 2 and SLR: 3 for PBlock: xdma_0_i_inst_pcie4_ip_i_inst_xdma_0_pcie4_ip_Stage1_main. SLLs required = 1, SLLs available = 0.
[Place 30-441] A placement could not be found which does not exceed the number of Super Long Lines (SLLs), 23040, for this device,
resulting in an unroutable situation.
Resolution: It is suggested to do one or more of the following techniques
to try to alleviate this situation:
1. Use a synthesis methodology that limits resource sharing across related hierarchies:
a. Prevent cross-boundary optimization on the complete design (synthesis option) or on specific hierarchical modules (attribute or constraint)
b. Bottom-up synthesis (Out-Of-Context, partitions)
c. Disable Resource Sharing and/or Equivalent Register Removal
2. Limit the use of high fanout nets in the design
3. Reevaluate pin placement for the design
4. Manually assign resources to Super Logic Regions (SLRs) ensuring connectivity is less than the maximum (define one pblock per SLR)
[Place 30-99] Placer failed with error: 'SSI partitioning failed!'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances

I don't kenow what's the error massage mains.

 

 

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Xilinx Employee
Xilinx Employee
180 Views
Registered: ‎05-22-2018

Re: Placement Error [Place 30-864]

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Hi @tinghao780609 ,

Please try to remove CONTAIN_ROUTING property from the PBLOCKS residing inside SLR. For reference please check this link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug912-vivado-properties.pdf#page=181

Thanks,

Raj

 

 

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2 Replies
Xilinx Employee
Xilinx Employee
181 Views
Registered: ‎05-22-2018

Re: Placement Error [Place 30-864]

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Hi @tinghao780609 ,

Please try to remove CONTAIN_ROUTING property from the PBLOCKS residing inside SLR. For reference please check this link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug912-vivado-properties.pdf#page=181

Thanks,

Raj

 

 

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Observer tinghao780609
Observer
165 Views
Registered: ‎12-09-2018

Re: Placement Error [Place 30-864]

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hi @rshekhaw 

It seem work on it, thanks a lot.

 

 

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